src/northbridge/intel/i440bx/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/romstage.h>
   4 #include <device/pci_ops.h>
   5 #include <cbmem.h>
   6 #include <commonlib/helpers.h>
   7 #include <cpu/x86/mtrr.h>
   8 #include <program_loading.h>
   9 #include "i440bx.h"
  10
  11 uintptr_t cbmem_top_chipset(void)
  12 {
  13         /* Base of TSEG is top of usable DRAM */
  14         /*
  15          * SMRAM - System Management RAM Control Register
  16          * 0x72
  17          * [7:4] Not relevant to this function.
  18          * [3:3] Global SMRAM Enable (G_SMRAME)
  19          * [2:0] Hardwired to 010.
  20          *
  21          * ESMRAMC - Extended System Management RAM Control
  22          * 0x73
  23          * [7:7] H_SMRAM_EN
  24          *       1 = When G_SMRAME=1, High SMRAM space is enabled at
  25          *           0x100A0000-0x100FFFFF and forwarded to DRAM address
  26          *           0x000A0000-0x000FFFFF.
  27          *       0 = When G_SMRAME=1, Compatible SMRAM space is enabled at
  28          *           0x000A0000-0x000BFFFF.
  29          * [6:3] Not relevant to this function.
  30          * [2:1] TSEG Size (T_SZ)
  31          *       Selects the size of the TSEG memory block, if enabled.
  32          *       00 = 128KiB
  33          *       01 = 256KiB
  34          *       10 = 512KiB
  35          *       11 = 1MiB
  36          * [0:0] TSEG_EN
  37          *       When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to
  38          *       appear between DRAM address (TOM-<TSEG Size>) to TOM.
  39          *
  40          * Source: 440BX datasheet, pages 3-28 thru 3-29.
  41          */
  42         uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB;
  43
  44         int gsmrame = pci_read_config8(NB, SMRAM) & 0x8;
  45         /* T_SZ and TSEG_EN */
  46         int tseg = pci_read_config8(NB, ESMRAMC) & 0x7;
  47         if ((tseg & 0x1) && gsmrame) {
  48                 int tseg_size = 128 * KiB * (1 << (tseg >> 1));
  49                 tom -= tseg_size;
  50         }
  51         return tom;
  52 }
  53
  54 void fill_postcar_frame(struct postcar_frame *pcf)
  55 {
  56         /* Cache CBMEM region as WB. */
  57         const uintptr_t top_of_ram = cbmem_top();
  58         postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
  59                 MTRR_TYPE_WRBACK);
  60 }