src/northbridge/intel/i945/raminit.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef RAMINIT_H
   4 #define RAMINIT_H
   5
   6 #include <types.h>
   7
   8 #define DIMM_SOCKETS 2
   9
  10 #define DIMM_TCO_BASE 0x30
  11
  12 /* Burst length is always 8 */
  13 #define BURSTLENGTH      8
  14
  15 struct sys_info {
  16         u16 memory_frequency;   /* 400, 533 or 667 */
  17         u16 fsb_frequency;      /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */
  18         u32 tclk;
  19
  20         u8 trp;
  21         u8 trcd;
  22         u8 tras;
  23         u8 trfc;
  24         u8 twr;
  25
  26         u8 cas;                 /* 3, 4 or 5 */
  27         u8 refresh;             /* 0 = 15.6us, 1 = 7.8us */
  28
  29         bool dual_channel;
  30         bool interleaved;
  31
  32         u8 mvco4x;              /* 0 (8x) or 1 (4x) */
  33         bool clkcfg_bit7;
  34         u8 boot_path;
  35 #define BOOT_PATH_NORMAL        0
  36 #define BOOT_PATH_RESET         1
  37 #define BOOT_PATH_RESUME        2
  38
  39         u8 package;             /* 0 = planar, 1 = stacked */
  40 #define SYSINFO_PACKAGE_PLANAR          0x00
  41 #define SYSINFO_PACKAGE_STACKED         0x01
  42         u8 dimm[2 * DIMM_SOCKETS];
  43         u8 rows[2 * DIMM_SOCKETS];
  44         u8 cols[2 * DIMM_SOCKETS];
  45 #define SYSINFO_DIMM_X16DS              0x00
  46 #define SYSINFO_DIMM_X8DS               0x01
  47 #define SYSINFO_DIMM_X16SS              0x02
  48 #define SYSINFO_DIMM_X8DDS              0x03
  49 #define SYSINFO_DIMM_NOT_POPULATED      0x04
  50
  51         u8 banks[2 * DIMM_SOCKETS];
  52         size_t banksize[2 * 2 * DIMM_SOCKETS];
  53         const u8 *spd_addresses;
  54
  55 } __packed;
  56
  57 void receive_enable_adjust(struct sys_info *sysinfo);
  58 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
  59 int fixup_i945gm_errata(void);
  60 #endif                          /* RAMINIT_H */