src/northbridge/intel/pineview/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/bootblock.h>
   4 #include <assert.h>
   5 #include <device/pci_ops.h>
   6 #include <types.h>
   7 #include "pineview.h"
   8
   9 static uint32_t encode_pciexbar_length(void)
  10 {
  11         switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
  12                 case 256: return 0 << 1;
  13                 case 128: return 1 << 1;
  14                 case  64: return 2 << 1;
  15                 default:  return dead_code_t(uint32_t);
  16         }
  17 }
  18
  19 void bootblock_early_northbridge_init(void)
  20 {
  21         const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
  22         pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
  23 }