src/northbridge/intel/pineview/pineview.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
   4 #define NORTHBRIDGE_INTEL_PINEVIEW_H
   5
   6 #include <southbridge/intel/i82801gx/i82801gx.h>
   7
   8 #define DEFAULT_PMIOBAR         0x00000400
   9
  10 #define BOOT_PATH_NORMAL        0
  11 #define BOOT_PATH_RESET         1
  12 #define BOOT_PATH_RESUME        2
  13
  14 /* Device 0:0.0 PCI configuration space (Host Bridge) */
  15 #define HOST_BRIDGE     PCI_DEV(0, 0, 0)
  16
  17 #include "hostbridge_regs.h"
  18
  19 /* Device 0:1.0 PCI configuration space (PCI Express) */
  20
  21 #define PEGSTS          0x214   /* 32 bits */
  22
  23 /* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */
  24 #define GMCH_IGD        PCI_DEV(0, 2, 0)
  25
  26 #define GMADR           0x18
  27 #define GTTADR          0x1c
  28 #define BSM             0x5c
  29
  30 /*
  31  * MCHBAR
  32  */
  33
  34 #include <northbridge/intel/common/fixed_bars.h>
  35
  36 /* As there are many registers, define them on a separate file */
  37
  38 #include "mchbar_regs.h"
  39
  40 void pineview_early_init(void);
  41 u32 decode_igd_memory_size(const u32 gms);
  42 u32 decode_igd_gtt_size(const u32 gsm);
  43
  44 /* Mainboard romstage callback functions */
  45 void get_mb_spd_addrmap(u8 *spd_addr_map);
  46 void mb_pirq_setup(void); /* optional */
  47
  48 #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */