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spd/lp5: Add Hynix memory part
[coreboot2.git] / src / northbridge / intel / sandybridge / raminit_native.c
blobed11945ebf11a7ea34064d1df903ee712d91cbd1
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <commonlib/bsd/clamp.h>
4 #include <console/console.h>
5 #include <console/usb.h>
6 #include <cpu/intel/model_206ax/model_206ax.h>
7 #include <delay.h>
8 #include <device/device.h>
9 #include <device/pci_def.h>
10 #include <device/pci_ops.h>
11 #include <northbridge/intel/sandybridge/chip.h>
12 #include <static.h>
13 #include <stdbool.h>
14 #include <stdint.h>
15
16 #include "sandybridge.h"
17 #include "raminit_common.h"
18 #include "raminit_tables.h"
19
20 #define SNB_MIN_DCLK_133_MULT 3
21 #define SNB_MAX_DCLK_133_MULT 8
22 #define IVB_MIN_DCLK_133_MULT 3
23 #define IVB_MAX_DCLK_133_MULT 10
24 #define IVB_MIN_DCLK_100_MULT 7
25 #define IVB_MAX_DCLK_100_MULT 12
26
27 /* Frequency multiplier */
28 static u32 get_FRQ(const ramctr_timing *ctrl)
29 {
30 const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq);
31
32 if (IS_IVY_CPU(ctrl->cpu)) {
33 if (ctrl->base_freq == 100)
34 return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT);
35
36 if (ctrl->base_freq == 133)
37 return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT);
38
39 } else if (IS_SANDY_CPU(ctrl->cpu)) {
40 if (ctrl->base_freq == 133)
41 return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT);
42 }
43
44 die("Unsupported CPU or base frequency.");
45 }
46
47 /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
48 static u8 get_CWL(u32 tCK)
49 {
50 /* Get CWL based on tCK using the following rule */
51 switch (tCK) {
52 case TCK_1333MHZ:
53 return 12;
54
55 case TCK_1200MHZ:
56 case TCK_1100MHZ:
57 return 11;
58
59 case TCK_1066MHZ:
60 case TCK_1000MHZ:
61 return 10;
62
63 case TCK_933MHZ:
64 case TCK_900MHZ:
65 return 9;
66
67 case TCK_800MHZ:
68 case TCK_700MHZ:
69 return 8;
70
71 case TCK_666MHZ:
72 return 7;
73
74 case TCK_533MHZ:
75 return 6;
76
77 default:
78 return 5;
79 }
80 }
81
82 /* Get REFI based on frequency index, tREFI = 7.8usec */
83 static u32 get_REFI(u32 FRQ, u8 base_freq)
84 {
85 if (base_freq == 100)
86 return frq_refi_map[1][FRQ - 7];
87
88 else
89 return frq_refi_map[0][FRQ - 3];
90 }
91
92 /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */
93 static u8 get_XSOffset(u32 FRQ, u8 base_freq)
94 {
95 if (base_freq == 100)
96 return frq_xs_map[1][FRQ - 7];
97
98 else
99 return frq_xs_map[0][FRQ - 3];
100 }
101
102 /* Get MOD based on frequency index */
103 static u8 get_MOD(u32 FRQ, u8 base_freq)
104 {
105 if (base_freq == 100)
106 return frq_mod_map[1][FRQ - 7];
107
108 else
109 return frq_mod_map[0][FRQ - 3];
110 }
111
112 /* Get Write Leveling Output delay based on frequency index */
113 static u8 get_WLO(u32 FRQ, u8 base_freq)
114 {
115 if (base_freq == 100)
116 return frq_wlo_map[1][FRQ - 7];
117
118 else
119 return frq_wlo_map[0][FRQ - 3];
120 }
121
122 /* Get CKE based on frequency index */
123 static u8 get_CKE(u32 FRQ, u8 base_freq)
124 {
125 if (base_freq == 100)
126 return frq_cke_map[1][FRQ - 7];
127
128 else
129 return frq_cke_map[0][FRQ - 3];
130 }
131
132 /* Get XPDLL based on frequency index */
133 static u8 get_XPDLL(u32 FRQ, u8 base_freq)
134 {
135 if (base_freq == 100)
136 return frq_xpdll_map[1][FRQ - 7];
137
138 else
139 return frq_xpdll_map[0][FRQ - 3];
140 }
141
142 /* Get XP based on frequency index */
143 static u8 get_XP(u32 FRQ, u8 base_freq)
144 {
145 if (base_freq == 100)
146 return frq_xp_map[1][FRQ - 7];
147
148 else
149 return frq_xp_map[0][FRQ - 3];
150 }
151
152 /* Get AONPD based on frequency index */
153 static u8 get_AONPD(u32 FRQ, u8 base_freq)
154 {
155 if (base_freq == 100)
156 return frq_aonpd_map[1][FRQ - 7];
157
158 else
159 return frq_aonpd_map[0][FRQ - 3];
160 }
161
162 /* Get COMP2 based on CPU generation and clock speed */
163 static u32 get_COMP2(const ramctr_timing *ctrl)
164 {
165 const bool is_ivybridge = IS_IVY_CPU(ctrl->cpu);
166
167 if (ctrl->tCK <= TCK_1066MHZ)
168 return is_ivybridge ? 0x0C235924 : 0x0C21410C;
169 else if (ctrl->tCK <= TCK_933MHZ)
170 return is_ivybridge ? 0x0C446964 : 0x0C42514C;
171 else if (ctrl->tCK <= TCK_800MHZ)
172 return is_ivybridge ? 0x0C6671E4 : 0x0C6369CC;
173 else if (ctrl->tCK <= TCK_666MHZ)
174 return is_ivybridge ? 0x0CA8C264 : 0x0CA57A4C;
175 else if (ctrl->tCK <= TCK_533MHZ)
176 return is_ivybridge ? 0x0CEBDB64 : 0x0CE7C34C;
177 else
178 return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC;
179 }
180
181 /* Get updated COMP1 based on CPU generation and stepping */
182 static u32 get_COMP1(ramctr_timing *ctrl, const int channel)
183 {
184 const union comp_ofst_1_reg orig_comp = {
185 .raw = mchbar_read32(CRCOMPOFST1_ch(channel)),
186 };
187
188 if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) {
189 union comp_ofst_1_reg comp_ofst_1 = orig_comp;
190
191 comp_ofst_1.clk_odt_up = 1;
192 comp_ofst_1.clk_drv_up = 1;
193 comp_ofst_1.ctl_drv_up = 1;
194
195 return comp_ofst_1.raw;
196 }
197
198 /* Fix PCODE COMP offset bug: revert to default values */
199 union comp_ofst_1_reg comp_ofst_1 = {
200 .dq_odt_down = 4,
201 .dq_odt_up = 4,
202 .clk_odt_down = 4,
203 .clk_odt_up = orig_comp.clk_odt_up,
204 .dq_drv_down = 4,
205 .dq_drv_up = orig_comp.dq_drv_up,
206 .clk_drv_down = 4,
207 .clk_drv_up = orig_comp.clk_drv_up,
208 .ctl_drv_down = 4,
209 .ctl_drv_up = orig_comp.ctl_drv_up,
210 };
211
212 if (IS_IVY_CPU(ctrl->cpu))
213 comp_ofst_1.dq_drv_up = 2; /* 28p6 ohms */
214
215 return comp_ofst_1.raw;
216 }
217
218 static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support)
219 {
220 if (ctrl->tCK <= TCK_1200MHZ) {
221 ctrl->tCK = TCK_1200MHZ;
222 ctrl->base_freq = 133;
223 } else if (ctrl->tCK <= TCK_1100MHZ) {
224 ctrl->tCK = TCK_1100MHZ;
225 ctrl->base_freq = 100;
226 } else if (ctrl->tCK <= TCK_1066MHZ) {
227 ctrl->tCK = TCK_1066MHZ;
228 ctrl->base_freq = 133;
229 } else if (ctrl->tCK <= TCK_1000MHZ) {
230 ctrl->tCK = TCK_1000MHZ;
231 ctrl->base_freq = 100;
232 } else if (ctrl->tCK <= TCK_933MHZ) {
233 ctrl->tCK = TCK_933MHZ;
234 ctrl->base_freq = 133;
235 } else if (ctrl->tCK <= TCK_900MHZ) {
236 ctrl->tCK = TCK_900MHZ;
237 ctrl->base_freq = 100;
238 } else if (ctrl->tCK <= TCK_800MHZ) {
239 ctrl->tCK = TCK_800MHZ;
240 ctrl->base_freq = 133;
241 } else if (ctrl->tCK <= TCK_700MHZ) {
242 ctrl->tCK = TCK_700MHZ;
243 ctrl->base_freq = 100;
244 } else if (ctrl->tCK <= TCK_666MHZ) {
245 ctrl->tCK = TCK_666MHZ;
246 ctrl->base_freq = 133;
247 } else if (ctrl->tCK <= TCK_533MHZ) {
248 ctrl->tCK = TCK_533MHZ;
249 ctrl->base_freq = 133;
250 } else if (ctrl->tCK <= TCK_400MHZ) {
251 ctrl->tCK = TCK_400MHZ;
252 ctrl->base_freq = 133;
253 } else {
254 ctrl->tCK = 0;
255 return;
256 }
257
258 if (!ref_100mhz_support && ctrl->base_freq == 100) {
259 /* Skip unsupported frequency */
260 ctrl->tCK++;
261 normalize_tclk(ctrl, ref_100mhz_support);
262 }
263 }
264
265 #define DEFAULT_TCK TCK_800MHZ
266
267 static unsigned int get_mem_min_tck(void)
268 {
269 u32 reg32;
270 u8 rev;
271 const struct northbridge_intel_sandybridge_config *cfg = NULL;
272
273 /* Actually, config of MCH or Host Bridge */
274 cfg = config_of_soc();
275
276 /* If non-zero, it was set in the devicetree */
277 if (cfg->max_mem_clock_mhz) {
278 if (cfg->max_mem_clock_mhz >= 1066)
279 return TCK_1066MHZ;
280
281 else if (cfg->max_mem_clock_mhz >= 933)
282 return TCK_933MHZ;
283
284 else if (cfg->max_mem_clock_mhz >= 800)
285 return TCK_800MHZ;
286
287 else if (cfg->max_mem_clock_mhz >= 666)
288 return TCK_666MHZ;
289
290 else if (cfg->max_mem_clock_mhz >= 533)
291 return TCK_533MHZ;
292
293 else
294 return TCK_400MHZ;
295 }
296
297 if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
298 return TCK_1333MHZ;
299
300 rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
301
302 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
303 /* Read Capabilities A Register DMFC bits */
304 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A);
305 reg32 &= 0x7;
306
307 switch (reg32) {
308 case 7: return TCK_533MHZ;
309 case 6: return TCK_666MHZ;
310 case 5: return TCK_800MHZ;
311 /* Reserved */
312 default:
313 break;
314 }
315 } else {
316 /* Read Capabilities B Register DMFC bits */
317 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
318 reg32 = (reg32 >> 4) & 0x7;
319
320 switch (reg32) {
321 case 7: return TCK_533MHZ;
322 case 6: return TCK_666MHZ;
323 case 5: return TCK_800MHZ;
324 case 4: return TCK_933MHZ;
325 case 3: return TCK_1066MHZ;
326 case 2: return TCK_1200MHZ;
327 case 1: return TCK_1333MHZ;
328 /* Reserved */
329 default:
330 break;
331 }
332 }
333 return DEFAULT_TCK;
334 }
335
336 static void find_cas_tck(ramctr_timing *ctrl)
337 {
338 u8 val;
339 u32 reg32;
340 u8 ref_100mhz_support;
341
342 /* 100 MHz reference clock supported */
343 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
344 ref_100mhz_support = (reg32 >> 21) & 0x7;
345 printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes"
346 : "no");
347
348 printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
349
350 ctrl->tCK = get_mem_min_tck();
351
352 /* Find CAS latency */
353 while (1) {
354 /*
355 * Normalising tCK before computing clock could potentially
356 * result in a lower selected CAS, which is desired.
357 */
358 normalize_tclk(ctrl, ref_100mhz_support);
359 if (!(ctrl->tCK))
360 die("Couldn't find compatible clock / CAS settings\n");
361
362 val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
363 printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK);
364 for (; val <= MAX_CAS; val++)
365 if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1)
366 break;
367
368 if (val == (MAX_CAS + 1)) {
369 ctrl->tCK++;
370 continue;
371 } else {
372 printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n");
373 break;
374 }
375 }
376
377 /* Frequency multiplier */
378 ctrl->FRQ = get_FRQ(ctrl);
379
380 printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
381 printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val);
382 ctrl->CAS = val;
383 }
384
385 static void dram_timing(ramctr_timing *ctrl)
386 {
387 /*
388 * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133).
389 * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency.
390 */
391 /*
392 * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800).
393 * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency.
394 */
395 if (ctrl->tCK == TCK_1200MHZ) {
396 ctrl->edge_offset[0] = 18; //XXX: guessed
397 ctrl->edge_offset[1] = 8;
398 ctrl->edge_offset[2] = 8;
399 ctrl->tx_dq_offset[0] = 20; //XXX: guessed
400 ctrl->tx_dq_offset[1] = 8;
401 ctrl->tx_dq_offset[2] = 8;
402 ctrl->pi_coding_threshold = 10;
403
404 } else if (ctrl->tCK == TCK_1100MHZ) {
405 ctrl->edge_offset[0] = 17; //XXX: guessed
406 ctrl->edge_offset[1] = 7;
407 ctrl->edge_offset[2] = 7;
408 ctrl->tx_dq_offset[0] = 19; //XXX: guessed
409 ctrl->tx_dq_offset[1] = 7;
410 ctrl->tx_dq_offset[2] = 7;
411 ctrl->pi_coding_threshold = 13;
412
413 } else if (ctrl->tCK == TCK_1066MHZ) {
414 ctrl->edge_offset[0] = 16;
415 ctrl->edge_offset[1] = 7;
416 ctrl->edge_offset[2] = 7;
417 ctrl->tx_dq_offset[0] = 18;
418 ctrl->tx_dq_offset[1] = 7;
419 ctrl->tx_dq_offset[2] = 7;
420 ctrl->pi_coding_threshold = 13;
421
422 } else if (ctrl->tCK == TCK_1000MHZ) {
423 ctrl->edge_offset[0] = 15; //XXX: guessed
424 ctrl->edge_offset[1] = 6;
425 ctrl->edge_offset[2] = 6;
426 ctrl->tx_dq_offset[0] = 17; //XXX: guessed
427 ctrl->tx_dq_offset[1] = 6;
428 ctrl->tx_dq_offset[2] = 6;
429 ctrl->pi_coding_threshold = 13;
430
431 } else if (ctrl->tCK == TCK_933MHZ) {
432 ctrl->edge_offset[0] = 14;
433 ctrl->edge_offset[1] = 6;
434 ctrl->edge_offset[2] = 6;
435 ctrl->tx_dq_offset[0] = 15;
436 ctrl->tx_dq_offset[1] = 6;
437 ctrl->tx_dq_offset[2] = 6;
438 ctrl->pi_coding_threshold = 15;
439
440 } else if (ctrl->tCK == TCK_900MHZ) {
441 ctrl->edge_offset[0] = 14; //XXX: guessed
442 ctrl->edge_offset[1] = 6;
443 ctrl->edge_offset[2] = 6;
444 ctrl->tx_dq_offset[0] = 15; //XXX: guessed
445 ctrl->tx_dq_offset[1] = 6;
446 ctrl->tx_dq_offset[2] = 6;
447 ctrl->pi_coding_threshold = 12;
448
449 } else if (ctrl->tCK == TCK_800MHZ) {
450 ctrl->edge_offset[0] = 13;
451 ctrl->edge_offset[1] = 5;
452 ctrl->edge_offset[2] = 5;
453 ctrl->tx_dq_offset[0] = 14;
454 ctrl->tx_dq_offset[1] = 5;
455 ctrl->tx_dq_offset[2] = 5;
456 ctrl->pi_coding_threshold = 15;
457
458 } else if (ctrl->tCK == TCK_700MHZ) {
459 ctrl->edge_offset[0] = 13; //XXX: guessed
460 ctrl->edge_offset[1] = 5;
461 ctrl->edge_offset[2] = 5;
462 ctrl->tx_dq_offset[0] = 14; //XXX: guessed
463 ctrl->tx_dq_offset[1] = 5;
464 ctrl->tx_dq_offset[2] = 5;
465 ctrl->pi_coding_threshold = 16;
466
467 } else if (ctrl->tCK == TCK_666MHZ) {
468 ctrl->edge_offset[0] = 10;
469 ctrl->edge_offset[1] = 4;
470 ctrl->edge_offset[2] = 4;
471 ctrl->tx_dq_offset[0] = 11;
472 ctrl->tx_dq_offset[1] = 4;
473 ctrl->tx_dq_offset[2] = 4;
474 ctrl->pi_coding_threshold = 16;
475
476 } else if (ctrl->tCK == TCK_533MHZ) {
477 ctrl->edge_offset[0] = 8;
478 ctrl->edge_offset[1] = 3;
479 ctrl->edge_offset[2] = 3;
480 ctrl->tx_dq_offset[0] = 9;
481 ctrl->tx_dq_offset[1] = 3;
482 ctrl->tx_dq_offset[2] = 3;
483 ctrl->pi_coding_threshold = 17;
484
485 } else { /* TCK_400MHZ */
486 ctrl->edge_offset[0] = 6;
487 ctrl->edge_offset[1] = 2;
488 ctrl->edge_offset[2] = 2;
489 ctrl->tx_dq_offset[0] = 6;
490 ctrl->tx_dq_offset[1] = 2;
491 ctrl->tx_dq_offset[2] = 2;
492 ctrl->pi_coding_threshold = 17;
493 }
494
495 /* Initial phase between CLK/CMD pins */
496 ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66;
497
498 /* DLL_CONFIG_MDLL_W_TIMER */
499 ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3;
500
501 if (ctrl->tCWL)
502 ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
503 else
504 ctrl->CWL = get_CWL(ctrl->tCK);
505
506 ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
507 ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
508 ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
509 ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
510 ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
511 ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
512 ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
513 ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
514 ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
515
516 ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq);
517 ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq);
518 ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq);
519 ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq);
520 ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq);
521 ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq);
522 ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq);
523 ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq);
524
525 printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);
526 printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
527 printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
528 printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
529 printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
530 printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
531 printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
532 printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
533 printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
534 printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
535 }
536
537 static void dram_freq(ramctr_timing *ctrl)
538 {
539 if (ctrl->tCK > TCK_400MHZ) {
540 printk(BIOS_ERR,
541 "DRAM frequency is under lowest supported frequency (400 MHz). "
542 "Increasing to 400 MHz as last resort.\n");
543 ctrl->tCK = TCK_400MHZ;
544 }
545
546 while (1) {
547 u8 val2;
548 u32 reg1 = 0;
549
550 /* Step 1 - Determine target MPLL frequency */
551 find_cas_tck(ctrl);
552
553 /*
554 * The MPLL will never lock if the requested frequency is already set.
555 * Exit early to prevent a system hang.
556 */
557 reg1 = mchbar_read32(MC_BIOS_DATA);
558 val2 = (u8)reg1;
559 if (val2)
560 return;
561
562 /* Step 2 - Request MPLL frequency through the PCU */
563 reg1 = ctrl->FRQ;
564 if (ctrl->base_freq == 100)
565 reg1 |= (1 << 8); /* Use 100MHz reference clock */
566
567 reg1 |= (1 << 31); /* Set running bit */
568 mchbar_write32(MC_BIOS_REQ, reg1);
569 int i = 0;
570 printk(BIOS_DEBUG, "MPLL busy... ");
571 while (reg1 & (1 << 31)) {
572 udelay(10);
573 i++;
574 reg1 = mchbar_read32(MC_BIOS_REQ);
575 }
576 printk(BIOS_DEBUG, "done in %d us\n", i * 10);
577
578 /* Step 3 - Verify lock frequency */
579 reg1 = mchbar_read32(MC_BIOS_DATA);
580 val2 = (u8)reg1;
581 if (val2 >= ctrl->FRQ) {
582 printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n",
583 (1000 << 8) / ctrl->tCK);
584 return;
585 }
586 printk(BIOS_DEBUG, "MPLL didn't lock. Retrying at lower frequency\n");
587 ctrl->tCK++;
588 }
589 }
590
591 static void dram_ioregs(ramctr_timing *ctrl)
592 {
593 int channel;
594
595 /* IO clock */
596 FOR_ALL_CHANNELS {
597 mchbar_write32(GDCRCLKRANKSUSED_ch(channel), ctrl->rankmap[channel]);
598 }
599
600 /* IO command */
601 FOR_ALL_CHANNELS {
602 mchbar_write32(GDCRCTLRANKSUSED_ch(channel), ctrl->rankmap[channel]);
603 }
604
605 /* IO control */
606 FOR_ALL_POPULATED_CHANNELS {
607 program_timings(ctrl, channel);
608 }
609
610 /* Perform RCOMP */
611 printram("RCOMP...");
612 while (!(mchbar_read32(RCOMP_TIMER) & (1 << 16)))
613 ;
614
615 printram("done\n");
616
617 /* Set COMP2 */
618 mchbar_write32(CRCOMPOFST2, get_COMP2(ctrl));
619 printram("COMP2 done\n");
620
621 /* Set COMP1 */
622 FOR_ALL_POPULATED_CHANNELS {
623 mchbar_write32(CRCOMPOFST1_ch(channel), get_COMP1(ctrl, channel));
624 }
625 printram("COMP1 done\n");
626
627 printram("FORCE RCOMP and wait 20us...");
628 mchbar_setbits32(M_COMP, 1 << 8);
629 udelay(20);
630 printram("done\n");
631 }
632
633 int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
634 {
635 int err;
636
637 printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n",
638 IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy",
639 fast_boot ? "fast boot" : "full initialization");
640
641 if (!fast_boot) {
642 /* Find fastest common supported parameters */
643 dram_find_common_params(ctrl);
644
645 dram_dimm_mapping(ctrl);
646 }
647
648 /* Set MPLL frequency */
649 dram_freq(ctrl);
650
651 if (!fast_boot) {
652 /* Calculate timings */
653 dram_timing(ctrl);
654 }
655
656 /* Set version register */
657 mchbar_write32(MRC_REVISION, 0xc04eb002);
658
659 /* Enable crossover */
660 dram_xover(ctrl);
661
662 /* Set timing and refresh registers */
663 dram_timing_regs(ctrl);
664
665 /* Power mode preset */
666 mchbar_write32(PM_THML_STAT, 0x5500);
667
668 /* Set scheduler chicken bits */
669 mchbar_write32(SCHED_CBIT, 0x10100005);
670
671 /* Set up watermarks and starvation counter */
672 set_wmm_behavior(ctrl->cpu);
673
674 /* Clear IO reset bit */
675 mchbar_clrbits32(MC_INIT_STATE_G, 1 << 5);
676
677 /* Set MAD-DIMM registers */
678 dram_dimm_set_mapping(ctrl, 1);
679 printk(BIOS_DEBUG, "Done dimm mapping\n");
680
681 /* Zone config */
682 dram_zones(ctrl, 1);
683
684 /* Set memory map */
685 dram_memorymap(ctrl, me_uma_size);
686 printk(BIOS_DEBUG, "Done memory map\n");
687
688 /* Set IO registers */
689 dram_ioregs(ctrl);
690 printk(BIOS_DEBUG, "Done io registers\n");
691
692 udelay(1);
693
694 if (fast_boot) {
695 restore_timings(ctrl);
696 } else {
697 /* Do JEDEC DDR3 reset sequence */
698 dram_jedecreset(ctrl);
699 printk(BIOS_DEBUG, "Done jedec reset\n");
700
701 /* MRS commands */
702 dram_mrscommands(ctrl);
703 printk(BIOS_DEBUG, "Done MRS commands\n");
704
705 /* Prepare for memory training */
706 prepare_training(ctrl);
707
708 err = receive_enable_calibration(ctrl);
709 if (err)
710 return err;
711
712 err = read_mpr_training(ctrl);
713 if (err)
714 return err;
715
716 err = write_training(ctrl);
717 if (err)
718 return err;
719
720 printram("CP5a\n");
721
722 printram("CP5b\n");
723
724 err = command_training(ctrl);
725 if (err)
726 return err;
727
728 printram("CP5c\n");
729
730 err = aggressive_read_training(ctrl);
731 if (err)
732 return err;
733
734 err = aggressive_write_training(ctrl);
735 if (err)
736 return err;
737
738 normalize_training(ctrl);
739 }
740
741 set_read_write_timings(ctrl);
742
743 if (!s3resume) {
744 err = channel_test(ctrl);
745 if (err)
746 return err;
747 }
748
749 /* Set MAD-DIMM registers */
750 dram_dimm_set_mapping(ctrl, 0);
751
752 return 0;
753 }
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