1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Include this file into a mainboard DSDT inside the PCI device
5 * "Northbridge Miscellaneous Control (Northbridge function 3)" and it
6 * will expose the temperature sensor of the processor as a thermal
9 * Families 10 through 14 and some family 15 CPUs are supported.
11 * If, for example, the NB Misc. Control device is on 0:18.3, include
16 * Name (_ADR, 0x00180003)
17 * #include <soc/amd/common/acpi/thermal_zone.asl>
21 * Do not include this if the board is affected by erratum 319 as the
22 * thermal sensor of Socket F/AM2+ processors may be unreliable.
23 * (Erratum 319 affects AM2+ boards, AM3 and later should be fine)
26 #ifndef K10TEMP_HOT_OFFSET
27 # define K10TEMP_HOT_OFFSET 50
30 #define K10TEMP_KELVIN_OFFSET 2732
31 #define K10TEMP_TLIMIT_OFFSET 520
33 OperationRegion (TCFG, PCI_Config, 0x64, 0x4)
34 Field (TCFG, ByteAcc, NoLock, Preserve) {
35 HTCE, 1, /* Hardware thermal control enable */
37 TLMT, 7, /* (LimitTmp - 52) / 0.5 */
41 OperationRegion (TCTL, PCI_Config, 0xa4, 0x4)
42 Field (TCTL, ByteAcc, NoLock, Preserve) {
44 TNOW, 11, /* CurTmp / 0.125 */
48 Name (_STR, Unicode ("AMD CPU Core Thermal Sensor"))
57 Method (_TMP) { /* Current temp in tenths degree Kelvin. */
60 Return (Local0 + K10TEMP_KELVIN_OFFSET)
64 * TLMT indicates threshold where HTC become active. That is the processor will limit
65 * P-State and power consumption in order to cool down.
67 Method (_PSV) { /* Passive temp in tenths degree Kelvin. */
70 Local0 += K10TEMP_TLIMIT_OFFSET
71 Return (Local0 + K10TEMP_KELVIN_OFFSET)
74 Method (_HOT) { /* Hot temp in tenths degree Kelvin. */
75 Return (_PSV + K10TEMP_HOT_OFFSET)
78 Method (_CRT) { /* Critical temp in tenths degree Kelvin. */
79 Return (_HOT + K10TEMP_HOT_OFFSET)