src/soc/amd/common/block/acpimmio/biosram.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpimmio.h>
   4 #include <amdblocks/biosram.h>
   5 #include <device/mmio.h>
   6 #include <stdint.h>
   7
   8 /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */
   9 #define BIOSRAM_AP_ENTRY                0xe8 /* 8 bytes */
  10 #define BIOSRAM_CBMEM_TOP               0xf0 /* 4 bytes */
  11 #define BIOSRAM_UMA_SIZE                0xf4 /* 4 bytes */
  12 #define BIOSRAM_UMA_BASE                0xf8 /* 8 bytes */
  13
  14 static uint8_t biosram_read8(uint8_t reg)
  15 {
  16         return read8(acpimmio_biosram + reg);
  17 }
  18
  19 static void biosram_write8(uint8_t reg, uint8_t value)
  20 {
  21         write8(acpimmio_biosram + reg, value);
  22 }
  23
  24 static uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */
  25 {
  26         return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg));
  27 }
  28
  29 static void biosram_write16(uint8_t reg, uint16_t value)
  30 {
  31         biosram_write8(reg, value & 0xff);
  32         value >>= 8;
  33         biosram_write8(reg + sizeof(uint8_t), value & 0xff);
  34 }
  35
  36 static uint32_t biosram_read32(uint8_t reg)
  37 {
  38         uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16;
  39         return value | biosram_read16(reg);
  40 }
  41
  42 static void biosram_write32(uint8_t reg, uint32_t value)
  43 {
  44         biosram_write16(reg, value & 0xffff);
  45         value >>= 16;
  46         biosram_write16(reg + sizeof(uint16_t), value & 0xffff);
  47 }
  48
  49 /* Access to BIOSRAM is only allowed through the abstractions below. */
  50
  51 void *get_ap_entry_ptr(void)
  52 {
  53         return (void *)biosram_read32(BIOSRAM_AP_ENTRY);
  54 }
  55
  56 void set_ap_entry_ptr(void *entry)
  57 {
  58         biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry);
  59 }
  60
  61 void backup_top_of_low_cacheable(uintptr_t ramtop)
  62 {
  63         biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
  64 }
  65
  66 uintptr_t restore_top_of_low_cacheable(void)
  67 {
  68         return biosram_read32(BIOSRAM_CBMEM_TOP);
  69 }
  70
  71 void save_uma_size(uint32_t size)
  72 {
  73         biosram_write32(BIOSRAM_UMA_SIZE, size);
  74 }
  75
  76 void save_uma_base(uint64_t base)
  77 {
  78         biosram_write32(BIOSRAM_UMA_BASE, (uint32_t)base);
  79         biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t)(base >> 32));
  80 }
  81
  82 uint32_t get_uma_size(void)
  83 {
  84         return biosram_read32(BIOSRAM_UMA_SIZE);
  85 }
  86
  87 uint64_t get_uma_base(void)
  88 {
  89         uint64_t base;
  90         base = biosram_read32(BIOSRAM_UMA_BASE);
  91         base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
  92         return base;
  93 }