src/soc/amd/common/block/cpu/mca/mcax.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/msr_zen.h>
   4 #include <cpu/x86/lapic.h>
   5 #include <cpu/x86/msr.h>
   6 #include <console/console.h>
   7 #include <types.h>
   8 #include "mca_common_defs.h"
   9
  10 /* The McaXEnable bit in the config registers of the available MCAX banks is already set by the
  11    FSP, so no need to set it here again. */
  12
  13 bool mca_skip_check(void)
  14 {
  15         /* On Zen-based CPUs/APUs the MCA(X) status register have a defined state even in the
  16            cold boot path, so no need to skip the check */
  17         return false;
  18 }
  19
  20 /* Print the contents of the MCAX registers for a given bank */
  21 void mca_print_error(unsigned int bank)
  22 {
  23         msr_t msr;
  24
  25         printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank,
  26                 mca_get_bank_name(bank));
  27
  28         msr = rdmsr(MCAX_CTL_MSR(bank));
  29         printk(BIOS_WARNING, "   MC%u_CTL =      %08x_%08x\n", bank, msr.hi, msr.lo);
  30         msr = rdmsr(MCAX_STATUS_MSR(bank));
  31         printk(BIOS_WARNING, "   MC%u_STATUS =   %08x_%08x\n", bank, msr.hi, msr.lo);
  32         msr = rdmsr(MCAX_ADDR_MSR(bank));
  33         printk(BIOS_WARNING, "   MC%u_ADDR =     %08x_%08x\n", bank, msr.hi, msr.lo);
  34         msr = rdmsr(MCAX_MISC0_MSR(bank));
  35         printk(BIOS_WARNING, "   MC%u_MISC0 =    %08x_%08x\n", bank, msr.hi, msr.lo);
  36         msr = rdmsr(MCAX_CONFIG_MSR(bank));
  37         printk(BIOS_WARNING, "   MC%u_CONFIG =   %08x_%08x\n", bank, msr.hi, msr.lo);
  38         msr = rdmsr(MCAX_IPID_MSR(bank));
  39         printk(BIOS_WARNING, "   MC%u_IPID =     %08x_%08x\n", bank, msr.hi, msr.lo);
  40         msr = rdmsr(MCAX_SYND_MSR(bank));
  41         printk(BIOS_WARNING, "   MC%u_SYND =     %08x_%08x\n", bank, msr.hi, msr.lo);
  42         msr = rdmsr(MCAX_DESTAT_MSR(bank));
  43         printk(BIOS_WARNING, "   MC%u_DESTAT =   %08x_%08x\n", bank, msr.hi, msr.lo);
  44         msr = rdmsr(MCAX_DEADDR_MSR(bank));
  45         printk(BIOS_WARNING, "   MC%u_DEADDR =   %08x_%08x\n", bank, msr.hi, msr.lo);
  46         msr = rdmsr(MCAX_MISC1_MSR(bank));
  47         printk(BIOS_WARNING, "   MC%u_MISC1 =    %08x_%08x\n", bank, msr.hi, msr.lo);
  48         msr = rdmsr(MCAX_MISC2_MSR(bank));
  49         printk(BIOS_WARNING, "   MC%u_MISC2 =    %08x_%08x\n", bank, msr.hi, msr.lo);
  50         msr = rdmsr(MCAX_MISC3_MSR(bank));
  51         printk(BIOS_WARNING, "   MC%u_MISC3 =    %08x_%08x\n", bank, msr.hi, msr.lo);
  52         msr = rdmsr(MCAX_MISC4_MSR(bank));
  53         printk(BIOS_WARNING, "   MC%u_MISC4 =    %08x_%08x\n", bank, msr.hi, msr.lo);
  54         msr = rdmsr(MCA_CTL_MASK_MSR(bank));
  55         printk(BIOS_WARNING, "   MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo);
  56 }