src/soc/amd/common/block/gpio/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi_pm.h>
   4 #include <device/mmio.h>
   5 #include <device/device.h>
   6 #include <console/console.h>
   7 #include <elog.h>
   8 #include <gpio.h>
   9 #include <amdblocks/acpi.h>
  10 #include <amdblocks/acpimmio.h>
  11 #include <amdblocks/gpio.h>
  12 #include <amdblocks/smi.h>
  13 #include <soc/smi.h>
  14 #include <assert.h>
  15 #include <string.h>
  16 #include <types.h>
  17
  18 /*
  19  * acpimmio_gpio0, acpimmio_remote_gpio and acpimmio_iomux are defined in
  20  * soc/amd/common/block/acpimmio/mmio_util.c and declared as extern variables/constants in
  21  * amdblocks/acpimmio.h which is included in this file.
  22  */
  23
  24 /* MMIO access of new-style GPIO bank configuration registers */
  25 static inline void *gpio_ctrl_ptr(gpio_t gpio_num)
  26 {
  27         if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER ||
  28                         /* Verstage on PSP would need to map acpimmio_remote_gpio */
  29                         (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE) ||
  30                         gpio_num < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER)
  31                 return acpimmio_gpio0 + gpio_num * sizeof(uint32_t);
  32         else
  33                 return acpimmio_remote_gpio +
  34                         (gpio_num - AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER) * sizeof(uint32_t);
  35 }
  36
  37 static inline uint32_t gpio_read32(gpio_t gpio_num)
  38 {
  39         return read32(gpio_ctrl_ptr(gpio_num));
  40 }
  41
  42 static inline void gpio_write32(gpio_t gpio_num, uint32_t value)
  43 {
  44         write32(gpio_ctrl_ptr(gpio_num), value);
  45 }
  46
  47 static inline void *gpio_mux_ptr(gpio_t gpio_num)
  48 {
  49         if (SOC_GPIO_TOTAL_PINS < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER ||
  50                         /* Verstage on PSP would need to map acpimmio_remote_gpio */
  51                         (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE) ||
  52                         gpio_num < AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER)
  53                 return acpimmio_iomux + gpio_num;
  54         else
  55                 return acpimmio_remote_gpio + AMD_GPIO_REMOTE_GPIO_MUX_OFFSET +
  56                         (gpio_num - AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER);
  57 }
  58
  59 static uint8_t get_gpio_mux(gpio_t gpio_num)
  60 {
  61         return read8(gpio_mux_ptr(gpio_num));
  62 }
  63
  64 static void set_gpio_mux(gpio_t gpio_num, uint8_t function)
  65 {
  66         write8(gpio_mux_ptr(gpio_num), function & AMD_GPIO_MUX_MASK);
  67         get_gpio_mux(gpio_num); /* Flush posted write */
  68 }
  69
  70 static int get_gpio_gevent(gpio_t gpio, const struct soc_amd_event *table,
  71                                 size_t items)
  72 {
  73         size_t i;
  74
  75         for (i = 0; i < items; i++) {
  76                 if ((table + i)->gpio == gpio)
  77                         return (int)(table + i)->event;
  78         }
  79         return -1;
  80 }
  81
  82 static void program_smi(uint32_t flags, unsigned int gevent_num)
  83 {
  84         uint8_t level;
  85
  86         if (!is_gpio_event_level_triggered(flags)) {
  87                 printk(BIOS_ERR, "%s - Only level trigger allowed for SMI!\n", __func__);
  88                 BUG();
  89                 return;
  90         }
  91
  92         if (is_gpio_event_active_high(flags))
  93                 level = SMI_SCI_LVL_HIGH;
  94         else
  95                 level = SMI_SCI_LVL_LOW;
  96
  97         configure_gevent_smi(gevent_num, SMI_MODE_SMI, level);
  98 }
  99
 100 /*
 101  * For each general purpose event, GPE, the choice of edge/level triggered
 102  * event is represented as a single bit in SMI_SCI_LEVEL register.
 103  *
 104  * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is
 105  * represented as a single bit in SMI_SCI_TRIG register.
 106  */
 107 static void program_sci(uint32_t flags, unsigned int gevent_num)
 108 {
 109         struct sci_source sci;
 110
 111         sci.scimap = gevent_num;
 112         sci.gpe = gevent_num;
 113
 114         if (is_gpio_event_level_triggered(flags))
 115                 sci.level = SMI_SCI_LVL;
 116         else
 117                 sci.level = SMI_SCI_EDG;
 118
 119         if (is_gpio_event_active_high(flags))
 120                 sci.direction = SMI_SCI_LVL_HIGH;
 121         else
 122                 sci.direction = SMI_SCI_LVL_LOW;
 123
 124         configure_scimap(&sci);
 125 }
 126
 127 static void gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or)
 128 {
 129         uint32_t reg;
 130
 131         reg = gpio_read32(gpio_num);
 132         reg &= mask;
 133         reg |= or;
 134         gpio_write32(gpio_num, reg);
 135 }
 136
 137 /* Set specified bits of a register to match those of ctrl. */
 138 static void gpio_setbits32(gpio_t gpio_num, uint32_t mask, uint32_t ctrl)
 139 {
 140         gpio_update32(gpio_num, ~mask, ctrl & mask);
 141 }
 142
 143 static void gpio_and32(gpio_t gpio_num, uint32_t mask)
 144 {
 145         gpio_update32(gpio_num, mask, 0);
 146 }
 147
 148 static void gpio_or32(gpio_t gpio_num, uint32_t or)
 149 {
 150         gpio_update32(gpio_num, 0xffffffff, or);
 151 }
 152
 153 static void master_switch_clr(uint32_t mask)
 154 {
 155         const gpio_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t);
 156         gpio_and32(master_reg, ~mask);
 157 }
 158
 159 static void master_switch_set(uint32_t or)
 160 {
 161         const gpio_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t);
 162         gpio_or32(master_reg, or);
 163 }
 164
 165 int gpio_get(gpio_t gpio_num)
 166 {
 167         uint32_t reg;
 168
 169         reg = gpio_read32(gpio_num);
 170         return !!(reg & GPIO_PIN_STS);
 171 }
 172
 173 void gpio_set(gpio_t gpio_num, int value)
 174 {
 175         gpio_setbits32(gpio_num, GPIO_OUTPUT_VALUE, value ? GPIO_OUTPUT_VALUE : 0);
 176 }
 177
 178 void gpio_input_pulldown(gpio_t gpio_num)
 179 {
 180         gpio_setbits32(gpio_num, GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE, GPIO_PULLDOWN_ENABLE);
 181 }
 182
 183 void gpio_input_pullup(gpio_t gpio_num)
 184 {
 185         gpio_setbits32(gpio_num, GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE, GPIO_PULLUP_ENABLE);
 186 }
 187
 188 void gpio_input(gpio_t gpio_num)
 189 {
 190         gpio_and32(gpio_num, ~(GPIO_PULL_MASK | GPIO_OUTPUT_ENABLE));
 191 }
 192
 193 void gpio_output(gpio_t gpio_num, int value)
 194 {
 195         /* set GPIO output value before setting the direction to output to avoid glitches */
 196         gpio_set(gpio_num, value);
 197         gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE);
 198 }
 199
 200 const char *gpio_acpi_path(gpio_t gpio)
 201 {
 202         return "\\_SB.GPIO";
 203 }
 204
 205 uint16_t gpio_acpi_pin(gpio_t gpio)
 206 {
 207         return gpio;
 208 }
 209
 210 void gpio_save_pin_registers(gpio_t gpio, struct soc_amd_gpio_register_save *save)
 211 {
 212         save->mux_value = get_gpio_mux(gpio);
 213         save->control_value = gpio_read32(gpio);
 214 }
 215
 216 void gpio_restore_pin_registers(gpio_t gpio, struct soc_amd_gpio_register_save *save)
 217 {
 218         set_gpio_mux(gpio, save->mux_value);
 219         gpio_write32(gpio, save->control_value);
 220         gpio_read32(gpio); /* Flush posted write */
 221 }
 222
 223 static void set_single_gpio(const struct soc_amd_gpio *g)
 224 {
 225         static const struct soc_amd_event *gev_tbl;
 226         static size_t gev_items;
 227         int gevent_num;
 228         const bool can_set_smi_flags = !((CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) &&
 229                         ENV_SEPARATE_VERSTAGE) ||
 230                         CONFIG(SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE));
 231
 232         set_gpio_mux(g->gpio, g->function);
 233
 234         gpio_setbits32(g->gpio, PAD_CFG_MASK, g->control);
 235         /* Clear interrupt and wake status (write 1-to-clear bits) */
 236         gpio_or32(g->gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS);
 237         if (g->flags == 0)
 238                 return;
 239
 240         /* Can't set SMI flags from PSP */
 241         if (!can_set_smi_flags)
 242                 return;
 243
 244         if (gev_tbl == NULL)
 245                 soc_get_gpio_event_table(&gev_tbl, &gev_items);
 246
 247         gevent_num = get_gpio_gevent(g->gpio, gev_tbl, gev_items);
 248         if (gevent_num < 0) {
 249                 printk(BIOS_WARNING, "GPIO pin %d has no associated gevent!\n",
 250                                      g->gpio);
 251                 return;
 252         }
 253
 254         if (g->flags & GPIO_FLAG_SMI) {
 255                 program_smi(g->flags, gevent_num);
 256         } else if (g->flags & GPIO_FLAG_SCI) {
 257                 program_sci(g->flags, gevent_num);
 258         }
 259 }
 260
 261 void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg,
 262                                         size_t base_num_pads,
 263                                         const struct soc_amd_gpio *override_cfg,
 264                                         size_t override_num_pads)
 265 {
 266         const struct soc_amd_gpio *c;
 267         size_t i, j;
 268
 269         if (!base_cfg || !base_num_pads)
 270                 return;
 271
 272         /*
 273          * Disable blocking wake/interrupt status generation while updating
 274          * debounce registers. Otherwise when a debounce register is updated
 275          * the whole GPIO controller will zero out all interrupt enable status
 276          * bits while the delay happens. This could cause us to drop the bits
 277          * due to the read-modify-write that happens on each register.
 278          *
 279          * Additionally disable interrupt generation so we don't get any
 280          * spurious interrupts while updating the registers.
 281          */
 282         master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN);
 283
 284         for (i = 0; i < base_num_pads; i++) {
 285                 c = &base_cfg[i];
 286                 /* Check if override exist for GPIO from the base configuration */
 287                 for (j = 0; override_cfg && j < override_num_pads; j++) {
 288                         if (c->gpio == override_cfg[j].gpio) {
 289                                 c = &override_cfg[j];
 290                                 break;
 291                         }
 292                 }
 293                 set_single_gpio(c);
 294         }
 295
 296         /*
 297          * Re-enable interrupt status generation.
 298          *
 299          * We leave MASK_STATUS disabled because the kernel may reconfigure the
 300          * debounce registers while the drivers load. This will cause interrupts
 301          * to be missed during boot.
 302          */
 303         master_switch_set(GPIO_INTERRUPT_EN);
 304 }
 305
 306 void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 307 {
 308         gpio_configure_pads_with_override(gpio_list_ptr, size, NULL, 0);
 309 }
 310
 311 int gpio_interrupt_status(gpio_t gpio)
 312 {
 313         uint32_t reg = gpio_read32(gpio);
 314
 315         if (reg & GPIO_INT_STATUS) {
 316                 /* Clear interrupt status, preserve wake status */
 317                 reg &= ~GPIO_WAKE_STATUS;
 318                 gpio_write32(gpio, reg);
 319                 return 1;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static void check_and_add_wake_gpio(gpio_t begin, gpio_t end, struct gpio_wake_state *state)
 326 {
 327         gpio_t i;
 328         uint32_t reg;
 329
 330         for (i = begin; i < end; i++) {
 331                 reg = gpio_read32(i);
 332                 if (!(reg & GPIO_WAKE_STATUS))
 333                         continue;
 334                 printk(BIOS_INFO, "GPIO %d woke system.\n", i);
 335                 if (state->num_valid_wake_gpios >= ARRAY_SIZE(state->wake_gpios))
 336                         continue;
 337                 state->wake_gpios[state->num_valid_wake_gpios++] = i;
 338         }
 339 }
 340
 341 static void check_gpios(uint32_t wake_stat, unsigned int bit_limit, gpio_t gpio_base,
 342                         struct gpio_wake_state *state)
 343 {
 344         unsigned int i;
 345         gpio_t begin;
 346         gpio_t end;
 347
 348         for (i = 0; i < bit_limit; i++) {
 349                 if (!(wake_stat & BIT(i)))
 350                         continue;
 351                 /* Each wake status register bit is for 4 GPIOs that then will be checked */
 352                 begin = gpio_base + i * 4;
 353                 end = begin + 4;
 354                 /* There is no gpio 63. */
 355                 if (begin == 60)
 356                         end = 63;
 357                 check_and_add_wake_gpio(begin, end, state);
 358         }
 359 }
 360
 361 void gpio_fill_wake_state(struct gpio_wake_state *state)
 362 {
 363         /* Turn the wake registers into "gpio" index to conform to existing API. */
 364         const gpio_t stat0 = GPIO_WAKE_STAT_0 / sizeof(uint32_t);
 365         const gpio_t stat1 = GPIO_WAKE_STAT_1 / sizeof(uint32_t);
 366         const gpio_t control_switch = GPIO_MASTER_SWITCH / sizeof(uint32_t);
 367
 368         memset(state, 0, sizeof(*state));
 369
 370         state->control_switch = gpio_read32(control_switch);
 371         state->wake_stat[0] = gpio_read32(stat0);
 372         state->wake_stat[1] = gpio_read32(stat1);
 373
 374         printk(BIOS_INFO, "GPIO Control Switch: 0x%08x, Wake Stat 0: 0x%08x, Wake Stat 1: 0x%08x\n",
 375                 state->control_switch, state->wake_stat[0], state->wake_stat[1]);
 376
 377         check_gpios(state->wake_stat[0], 32, 0, state);
 378         check_gpios(state->wake_stat[1], 14, 128, state);
 379 }
 380
 381 void gpio_add_events(void)
 382 {
 383         const struct chipset_power_state *ps;
 384         const struct gpio_wake_state *state;
 385         unsigned int i;
 386         unsigned int end;
 387
 388         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_ELOG) < 0)
 389                 return;
 390         state = &ps->gpio_state;
 391
 392         end = MIN(state->num_valid_wake_gpios, ARRAY_SIZE(state->wake_gpios));
 393         for (i = 0; i < end; i++)
 394                 elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, state->wake_gpios[i]);
 395 }