1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef AMD_BLOCK_CPU_H
4 #define AMD_BLOCK_CPU_H
9 #define MAX_CSTATE_COUNT 8
11 void early_cache_setup(void);
12 int get_cpu_count(void);
13 unsigned int get_threads_per_core(void);
14 void set_cstate_io_addr(void);
15 void write_resume_eip(void);
17 union pstate_msr
; /* proper definition is in soc/msr.h */
19 uint32_t get_uvolts_from_vid(uint16_t core_vid
);
20 uint32_t get_pstate_0_reg(void);
21 uint32_t get_pstate_latency(void);
22 uint32_t get_pstate_core_freq(union pstate_msr pstate_reg
);
23 uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg
);
24 const acpi_cstate_t
*get_cstate_config_data(size_t *size
);
26 #endif /* AMD_BLOCK_CPU_H */