ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
[coreboot2.git] / src / soc / amd / common / block / include / amdblocks / smi.h
blob6995bef0f3c1a6da65be563382b5039e72d7bf9f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef AMD_BLOCK_SMI_H
4 #define AMD_BLOCK_SMI_H
6 #include <types.h>
8 enum smi_mode {
9 SMI_MODE_DISABLE = 0,
10 SMI_MODE_SMI = 1,
11 SMI_MODE_NMI = 2,
12 SMI_MODE_IRQ13 = 3,
15 enum smi_sci_type {
16 INTERRUPT_NONE,
17 INTERRUPT_SCI,
18 INTERRUPT_SMI,
19 INTERRUPT_BOTH,
22 enum smi_sci_lvl {
23 SMI_SCI_LVL_LOW,
24 SMI_SCI_LVL_HIGH,
27 enum smi_sci_dir {
28 SMI_SCI_EDG,
29 SMI_SCI_LVL,
32 struct smi_sources_t {
33 int type;
34 void (*handler)(void);
37 struct sci_source {
38 uint8_t scimap; /* SCI source number */
39 uint8_t gpe; /* 32 GPEs */
40 uint8_t direction; /* Active High or Low, smi_sci_lvl */
41 uint8_t level; /* Edge or Level, smi_sci_dir */
44 void configure_smi(uint8_t smi_num, uint8_t mode);
45 void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
46 void configure_scimap(const struct sci_source *sci);
47 void disable_gevent_smi(uint8_t gevent);
48 void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
49 void clear_all_smi_status(void);
50 void clear_smi_sci_status(void);
51 void reset_psp_smi(void);
52 void configure_psp_smi(void);
54 #endif /* AMD_BLOCK_SMI_H */