src/soc/amd/common/block/lpc/espi_def.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef AMD_BLOCK_ESPI_DEF_H
   4 #define AMD_BLOCK_ESPI_DEF_H
   5
   6 #define ESPI_DN_TX_HDR0                         0x00
   7 #define ESPI_DN_TX_HDR1                         0x04
   8 #define ESPI_DN_TX_HDR2                         0x08
   9 #define ESPI_DN_TX_DATA                         0x0c
  10
  11 #define ESPI_MASTER_CAP                         0x2c
  12 #define  ESPI_VW_MAX_SIZE_SHIFT                 13
  13 #define  ESPI_VW_MAX_SIZE_MASK                  (0x3f << ESPI_VW_MAX_SIZE_SHIFT)
  14
  15 #define ESPI_GLOBAL_CONTROL_0                   0x30
  16 #define  ESPI_WAIT_CNT_SHIFT                    24
  17 #define  ESPI_WAIT_CNT_MASK                     (0x3f << ESPI_WAIT_CNT_SHIFT)
  18 #define  ESPI_WDG_CNT_SHIFT                     8
  19 #define  ESPI_WDG_CNT_MASK                      (0xffff << ESPI_WDG_CNT_SHIFT)
  20 #define  ESPI_AL_IDLE_TIMER_SHIFT               4
  21 #define  ESPI_AL_IDLE_TIMER_MASK                (0x7 << ESPI_AL_IDLE_TIMER_SHIFT)
  22 #define  ESPI_AL_STOP_EN                        (1 << 3)
  23 #define  ESPI_PR_CLKGAT_EN                      (1 << 2)
  24 #define  ESPI_WAIT_CHKEN                        (1 << 1)
  25 #define  ESPI_WDG_EN                            (1 << 0)
  26
  27 #define ESPI_GLOBAL_CONTROL_1                   0x34
  28 #define  ESPI_ALERT_ENABLE                      (1 << 20) /* Mendocino and later SoCs */
  29 #define  ESPI_RGCMD_INT_MAP_SHIFT               13
  30 #define  ESPI_RGCMD_INT_MAP_MASK                (0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
  31 #define    ESPI_RGCMD_INT(irq)                  ((irq) << ESPI_RGCMD_INT_MAP_SHIFT)
  32 #define    ESPI_RGCMD_INT_SMI                   (0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
  33 #define  ESPI_ERR_INT_MAP_SHIFT                 8
  34 #define  ESPI_ERR_INT_MAP_MASK                  (0x1f << ESPI_ERR_INT_MAP_SHIFT)
  35 #define    ESPI_ERR_INT(irq)                    ((irq) << ESPI_ERR_INT_MAP_SHIFT)
  36 #define    ESPI_ERR_INT_SMI                     (0x1f << ESPI_ERR_INT_MAP_SHIFT)
  37 #define  ESPI_SUB_DECODE_SLV_SHIFT              3
  38 #define  ESPI_SUB_DECODE_SLV_MASK               (0x3 << ESPI_SUB_DECODE_SLV_SHIFT)
  39 #define  ESPI_SUB_DECODE_EN                     (1 << 2)
  40 #define  ESPI_BUS_MASTER_EN                     (1 << 1)
  41 #define  ESPI_SW_RST                            (1 << 0)
  42
  43 /* bits in ESPI_DECODE 0x40 */
  44 #define  ESPI_DECODE_MMIO_RANGE_EXT_EN(range)   (1 << (((range) & 3) + 28))
  45 #define  ESPI_DECODE_IO_RANGE_EXT_EN(range)     (1 << ((range) + 16))
  46 #define  ESPI_DECODE_MMIO_RANGE_EN(range)       (1 << (((range) & 3) + 12))
  47 #define  ESPI_DECODE_IO_RANGE_EN(range)         (1 << (((range) & 3) + 8))
  48
  49 #define ESPI_IO_BASE_REG0                       0x44
  50 #define ESPI_IO_BASE_REG1                       0x48
  51 #define ESPI_IO_SIZE0                           0x4c
  52 #define ESPI_MMIO_BASE_REG0                     0x50
  53 #define ESPI_MMIO_BASE_REG1                     0x54
  54 #define ESPI_MMIO_BASE_REG2                     0x58
  55 #define ESPI_MMIO_BASE_REG3                     0x5c
  56 #define ESPI_MMIO_SIZE_REG0                     0x60
  57 #define ESPI_MMIO_SIZE_REG1                     0x64
  58
  59 #define ESPI_SLAVE0_INT_EN                      0x6c
  60 #define ESPI_SLAVE0_INT_STS                     0x70
  61 #define  ESPI_STATUS_DNCMD_COMPLETE             (1 << 28)
  62 #define  ESPI_STATUS_NON_FATAL_ERROR            (1 << 6)
  63 #define  ESPI_STATUS_FATAL_ERROR                (1 << 5)
  64 #define  ESPI_STATUS_NO_RESPONSE                (1 << 4)
  65 #define  ESPI_STATUS_CRC_ERR                    (1 << 2)
  66 #define  ESPI_STATUS_WAIT_TIMEOUT               (1 << 1)
  67 #define  ESPI_STATUS_BUS_ERROR                  (1 << 0)
  68
  69 /* The extended IO/MMIO decode ranges are only available in SoCs that select
  70    SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES */
  71 #define ESPI_IO_BASE_REG2                       0x80
  72 #define ESPI_IO_BASE_REG3                       0x84
  73 #define ESPI_IO_SIZE1                           0x88
  74 #define ESPI_IO_BASE_REG4                       0x8c
  75 #define ESPI_IO_BASE_REG5                       0x90
  76 #define ESPI_IO_SIZE2                           0x94
  77 #define ESPI_IO_BASE_REG6                       0xb0
  78 #define ESPI_IO_BASE_REG7                       0xb4
  79 #define ESPI_IO_SIZE3                           0xb8
  80 #define ESPI_MMIO_BASE_REG4                     0xbc
  81 #define ESPI_MMIO_SIZE_REG2                     0xc0
  82
  83 #define ESPI_RXVW_POLARITY                      0xac
  84
  85 #define ESPI_DECODE_RANGES_PER_REG_GROUP        4
  86 #define ESPI_DECODE_RANGE_TO_REG_GROUP(range)   ((range) / ESPI_DECODE_RANGES_PER_REG_GROUP)
  87 #define ESPI_DECODE_RANGE_TO_REG_OFFSET(range)  ((range) % ESPI_DECODE_RANGES_PER_REG_GROUP)
  88
  89 /* the range parameter needs to be < ESPI_DECODE_RANGES_PER_REG_GROUP */
  90 #define ESPI_IO_RANGE_BASE_REG(base, range)     ((base) + (range) * 2)
  91 #define ESPI_IO_RANGE_SIZE_REG(base, range)     ((base) + (range))
  92 #define ESPI_MMIO_RANGE_BASE_REG(base, range)   ((base) + (range) * 4)
  93 #define ESPI_MMIO_RANGE_SIZE_REG(base, range)   ((base) + (range) * 2)
  94
  95 #endif /* AMD_BLOCK_ESPI_DEF_H */