src/soc/amd/common/block/lpc/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/hpet.h>
   4 #include <arch/ioapic.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pnp.h>
   9 #include <device/pci_ops.h>
  10 #include <pc80/mc146818rtc.h>
  11 #include <pc80/isa-dma.h>
  12 #include <pc80/i8254.h>
  13 #include <pc80/i8259.h>
  14 #include <amdblocks/acpi.h>
  15 #include <amdblocks/acpimmio.h>
  16 #include <amdblocks/espi.h>
  17 #include <amdblocks/ioapic.h>
  18 #include <amdblocks/iomap.h>
  19 #include <amdblocks/lpc.h>
  20 #include <soc/iomap.h>
  21 #include <soc/lpc.h>
  22 #include <soc/southbridge.h>
  23
  24 static void setup_serirq(void)
  25 {
  26         u8 byte;
  27
  28         /* Set up SERIRQ, enable continuous mode */
  29         byte = PM_SERIRQ_NUM_BITS_21;
  30         if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
  31                 byte |= PM_SERIRQ_ENABLE;
  32         if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
  33                 byte |= PM_SERIRQ_MODE;
  34
  35         pm_write8(PM_SERIRQ_CONF, byte);
  36 }
  37
  38 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
  39 {
  40         *gsi = ACPI_SCI_IRQ;
  41         *irq = ACPI_SCI_IRQ;
  42         *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;
  43 }
  44
  45 static void fch_ioapic_init(void)
  46 {
  47         fch_enable_ioapic_decode();
  48         register_new_ioapic_gsi0(IO_APIC_ADDR);
  49 }
  50
  51 static void lpc_init(struct device *dev)
  52 {
  53         u8 byte;
  54
  55         /* Initialize isa dma */
  56         isa_dma_init();
  57
  58         /* Enable DMA transaction on the LPC bus */
  59         byte = pci_read_config8(dev, LPC_PCI_CONTROL);
  60         byte |= LEGACY_DMA_EN;
  61         pci_write_config8(dev, LPC_PCI_CONTROL, byte);
  62
  63         /* Disable the timeout mechanism on LPC */
  64         byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
  65         byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;
  66         pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
  67
  68         /* Disable LPC MSI Capability */
  69         byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);
  70         /* BIT 1 is not defined in public datasheet. */
  71         byte &= ~(1 << 1);
  72
  73         pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
  74
  75         /*
  76          * Enable hand-instance of the pulse generator and SPI prefetch from
  77          * host (earlier is recommended for boot speed).
  78          */
  79         byte = pci_read_config8(dev, LPC_HOST_CONTROL);
  80         byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
  81         pci_write_config8(dev, LPC_HOST_CONTROL, byte);
  82
  83         cmos_check_update_date();
  84
  85         /*
  86          * Initialize the real time clock.
  87          * The 0 argument tells cmos_init not to
  88          * update CMOS unless it is invalid.
  89          * 1 tells cmos_init to always initialize the CMOS.
  90          */
  91         cmos_init(0);
  92
  93         /* Initialize i8259 pic */
  94         setup_i8259();
  95
  96         /* Initialize i8254 timers */
  97         setup_i8254();
  98
  99         setup_serirq();
 100
 101         fch_ioapic_init();
 102         fch_configure_hpet();
 103 }
 104
 105 static void lpc_read_resources(struct device *dev)
 106 {
 107         unsigned long idx = 0;
 108
 109         /* Get the normal pci resources of this device */
 110         pci_dev_read_resources(dev);
 111
 112         /* Add an extra subtractive resource for I/O. */
 113         fixed_io_range_flags(dev, IOINDEX_SUBTRACTIVE(0, 0), 0, 0x1000,
 114                              IORESOURCE_SUBTRACTIVE);
 115
 116         /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
 117         mmio_range(dev, idx++, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
 118                    FLASH_BELOW_4GB_MAPPING_REGION_SIZE);
 119
 120         /* Add a memory resource for the SPI BAR. */
 121         mmio_range(dev, idx++, SPI_BASE_ADDRESS, 4 * KiB);
 122
 123         /* Add a memory resource for the eSPI MMIO */
 124         mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
 125
 126         /* FCH IOAPIC */
 127         mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);
 128
 129         /* HPET */
 130         mmio_range(dev, idx++, HPET_BASE_ADDRESS, 4 * KiB);
 131
 132         compact_resources(dev);
 133 }
 134
 135 static void configure_child_lpc_windows(struct device *dev, struct device *child)
 136 {
 137         struct resource *res;
 138         u32 base, end;
 139         u32 rsize = 0, set = 0, set_x = 0;
 140         int wideio_index;
 141         u32 reg, reg_x;
 142
 143         reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE);
 144         reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 145
 146         /*
 147          * Be a bit relaxed, tolerate that LPC region might be bigger than
 148          * resource we try to fit, do it like this for all regions < 16 bytes.
 149          * If there is a resource > 16 bytes it must be 512 bytes to be able
 150          * to allocate the fresh LPC window.
 151          *
 152          * AGESA and early initialization can set a wide IO port. This code
 153          * will verify if required region was previously set and will avoid
 154          * setting a new wide IO resource if one is already set.
 155          */
 156
 157         for (res = child->resource_list; res; res = res->next) {
 158                 if (!(res->flags & IORESOURCE_IO))
 159                         continue;
 160                 base = res->base;
 161                 end = resource_end(res);
 162                 printk(BIOS_DEBUG,
 163                         "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n",
 164                         dev_path(child), base, end);
 165                 /* find a resource size */
 166                 switch (base) {
 167                 case 0x60:      /*  KB */
 168                 case 0x64:      /*  MS */
 169                         set |= DECODE_ENABLE_KBC_PORT;
 170                         rsize = 1;
 171                         break;
 172                 case 0x3f8:     /*  COM1 */
 173                         set |= DECODE_ENABLE_SERIAL_PORT0;
 174                         rsize = 8;
 175                         break;
 176                 case 0x2f8:     /*  COM2 */
 177                         set |= DECODE_ENABLE_SERIAL_PORT1;
 178                         rsize = 8;
 179                         break;
 180                 case 0x378:     /*  Parallel 1 */
 181                         set |= DECODE_ENABLE_PARALLEL_PORT0;
 182                         /* enable 0x778 for ECP mode */
 183                         set |= DECODE_ENABLE_PARALLEL_PORT1;
 184                         rsize = 8;
 185                         break;
 186                 case 0x3f0:     /*  FD0 */
 187                         set |= DECODE_ENABLE_FDC_PORT0;
 188                         rsize = 8;
 189                         break;
 190                 case 0x220:     /*  0x220 - 0x227 */
 191                         set |= DECODE_ENABLE_SERIAL_PORT2;
 192                         rsize = 8;
 193                         break;
 194                 case 0x228:     /*  0x228 - 0x22f */
 195                         set |= DECODE_ENABLE_SERIAL_PORT3;
 196                         rsize = 8;
 197                         break;
 198                 case 0x238:     /*  0x238 - 0x23f */
 199                         set |= DECODE_ENABLE_SERIAL_PORT4;
 200                         rsize = 8;
 201                         break;
 202                 case 0x300:     /*  0x300 - 0x301 */
 203                         set |= DECODE_ENABLE_MIDI_PORT0;
 204                         rsize = 2;
 205                         break;
 206                 case 0x400:
 207                         set_x |= DECODE_IO_PORT_ENABLE0;
 208                         rsize = 0x40;
 209                         break;
 210                 case 0x480:
 211                         set_x |= DECODE_IO_PORT_ENABLE1;
 212                         rsize = 0x40;
 213                         break;
 214                 case 0x500:
 215                         set_x |= DECODE_IO_PORT_ENABLE2;
 216                         rsize = 0x40;
 217                         break;
 218                 case 0x580:
 219                         set_x |= DECODE_IO_PORT_ENABLE3;
 220                         rsize = 0x40;
 221                         break;
 222                 case 0x4700:
 223                         set_x |= DECODE_IO_PORT_ENABLE5;
 224                         rsize = 0xc;
 225                         break;
 226                 case 0xfd60:
 227                         set_x |= DECODE_IO_PORT_ENABLE6;
 228                         rsize = 16;
 229                         break;
 230                 default:
 231                         rsize = 0;
 232                         wideio_index = lpc_find_wideio_range(base, res->size);
 233                         if (wideio_index != WIDEIO_RANGE_ERROR) {
 234                                 rsize = lpc_wideio_size(wideio_index);
 235                                 printk(BIOS_DEBUG, "Covered by wideIO");
 236                                 printk(BIOS_DEBUG, " %d\n", wideio_index);
 237                         }
 238                 }
 239                 /* check if region found and matches the enable */
 240                 if (res->size <= rsize) {
 241                         reg |= set;
 242                         reg_x |= set_x;
 243                 /* check if we can fit resource in variable range */
 244                 } else {
 245                         wideio_index = lpc_set_wideio_range(base, res->size);
 246                         if (wideio_index != WIDEIO_RANGE_ERROR) {
 247                                 /* preserve wide IO related bits. */
 248                                 reg_x = pci_read_config32(dev,
 249                                         LPC_IO_OR_MEM_DECODE_ENABLE);
 250                                 printk(BIOS_DEBUG,
 251                                         "Range assigned to wide IO %d\n",
 252                                         wideio_index);
 253                         } else {
 254                                 printk(BIOS_ERR,
 255                                         "cannot fit LPC decode region:");
 256                                 printk(BIOS_ERR,
 257                                         "%s, base = 0x%08x, end = 0x%08x\n",
 258                                         dev_path(child), base, end);
 259                         }
 260                 }
 261         }
 262
 263         pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg);
 264         pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x);
 265 }
 266
 267 static void configure_child_espi_windows(struct device *child)
 268 {
 269         struct resource *res;
 270
 271         for (res = child->resource_list; res; res = res->next) {
 272                 if (res->flags & IORESOURCE_IO)
 273                         espi_open_io_window(res->base, res->size);
 274                 else if (res->flags & IORESOURCE_MEM)
 275                         espi_open_mmio_window(res->base, res->size);
 276         }
 277 }
 278
 279 static void lpc_enable_children_resources(struct device *dev)
 280 {
 281         struct device *child;
 282
 283         if (!dev->downstream)
 284                 return;
 285
 286         for (child = dev->downstream->children; child; child = child->sibling) {
 287                 if (!child->enabled)
 288                         continue;
 289                 if (child->path.type != DEVICE_PATH_PNP)
 290                         continue;
 291                 if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
 292                         configure_child_espi_windows(child);
 293                 else
 294                         configure_child_lpc_windows(dev, child);
 295         }
 296 }
 297
 298 static void lpc_enable_resources(struct device *dev)
 299 {
 300         pci_dev_enable_resources(dev);
 301         lpc_enable_children_resources(dev);
 302 }
 303
 304 #if CONFIG(HAVE_ACPI_TABLES)
 305 static const char *lpc_acpi_name(const struct device *dev)
 306 {
 307         return "LPCB";
 308 }
 309 #endif
 310
 311 struct device_operations amd_lpc_ops = {
 312         .read_resources = lpc_read_resources,
 313         .set_resources = pci_dev_set_resources,
 314         .enable_resources = lpc_enable_resources,
 315 #if CONFIG(HAVE_ACPI_TABLES)
 316         .acpi_name = lpc_acpi_name,
 317         .write_acpi_tables = southbridge_write_acpi_tables,
 318 #endif
 319         .init = lpc_init,
 320         .scan_bus = scan_static_bus,
 321         .ops_pci = &pci_dev_ops_pci,
 322 };