src/soc/amd/common/block/psp/psp_def.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __AMD_PSP_DEF_H__
   4 #define __AMD_PSP_DEF_H__
   5
   6 #include <types.h>
   7 #include <commonlib/helpers.h>
   8 #include <amdblocks/psp.h>
   9
  10 #define CORE_2_PSP_MSG_38_OFFSET        0x10998 /* 4 byte */
  11 #define   CORE_2_PSP_MSG_38_FUSE_SPL            BIT(12)
  12 #define   CORE_2_PSP_MSG_38_SPL_FUSE_ERROR      BIT(13)
  13 #define   CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR     BIT(14)
  14 #define   CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING   BIT(15)
  15
  16 /* x86 to PSP commands */
  17 #define MBOX_BIOS_CMD_SMM_INFO                  0x02
  18 #define MBOX_BIOS_CMD_SX_INFO                   0x03
  19 #define   MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX  0x07
  20 #define MBOX_BIOS_CMD_RSM_INFO                  0x04
  21 #define MBOX_BIOS_CMD_PSP_FTPM_QUERY            0x05
  22 #define MBOX_BIOS_CMD_BOOT_DONE                 0x06
  23 #define MBOX_BIOS_CMD_CLEAR_S3_STS              0x07
  24 #define MBOX_BIOS_CMD_S3_DATA_INFO              0x08
  25 #define MBOX_BIOS_CMD_NOP                       0x09
  26 #define MBOX_BIOS_CMD_HSTI_QUERY                0x14
  27 #define MBOX_BIOS_CMD_PSB_AUTO_FUSING           0x21
  28 #define MBOX_BIOS_CMD_PSP_CAPS_QUERY            0x27
  29 #define MBOX_BIOS_CMD_SET_SPL_FUSE              0x2d
  30 #define MBOX_BIOS_CMD_SET_RPMC_ADDRESS          0x39
  31 #define MBOX_BIOS_CMD_QUERY_SPL_FUSE            0x47
  32 #define MBOX_BIOS_CMD_I2C_TPM_ARBITRATION       0x64
  33 #define MBOX_BIOS_CMD_ABORT                     0xfe
  34
  35 /* x86 to PSP commands, v1-only */
  36 #define MBOX_BIOS_CMD_DRAM_INFO                 0x01
  37 #define MBOX_BIOS_CMD_SMU_FW                    0x19
  38 #define MBOX_BIOS_CMD_SMU_FW2                   0x1a
  39
  40 #define SMN_PSP_PUBLIC_BASE                     0x3800000
  41
  42 /* command/response format, BIOS builds this in memory
  43  *   mbox_buffer_header: generic header
  44  *   mbox_buffer:        command-specific buffer format
  45  *
  46  * AMD reference code aligns and pads all buffers to 32 bytes.
  47  */
  48 struct mbox_buffer_header {
  49         uint32_t size;          /* total size of buffer */
  50         uint32_t status;        /* command status, filled by PSP if applicable */
  51 } __packed;
  52
  53 /*
  54  * x86 to PSP mailbox commands that don't take any parameter or return any data, use the
  55  * mbox_default_buffer, while x86 to PSP commands that either pass data to the PSP or get data
  56  * returned from the PSP use command-specific buffer definitions. For details on the specific
  57  * buffer definitions for the various commands, see NDA document #54267 for the generations
  58  * before family 17h and NDA document #55758 for the generations from family 17h on.
  59  */
  60
  61 struct mbox_default_buffer {    /* command-response buffer unused by command */
  62         struct mbox_buffer_header header;
  63 } __packed __aligned(32);
  64
  65 struct smm_req_buffer {
  66         uint64_t smm_base;              /* TSEG base */
  67         uint64_t smm_mask;              /* TSEG mask */
  68         uint64_t psp_smm_data_region;   /* PSP region in SMM space */
  69         uint64_t psp_smm_data_length;   /* PSP region length in SMM space */
  70         struct smm_trigger_info smm_trig_info;
  71 #if CONFIG(SOC_AMD_COMMON_BLOCK_PSP_GEN2)
  72         struct smm_register_info smm_reg_info;
  73 #endif
  74         uint64_t psp_mbox_smm_buffer_address;
  75         uint64_t psp_mbox_smm_flag_address;
  76 } __packed;
  77
  78 /* MBOX_BIOS_CMD_SMM_INFO */
  79 struct mbox_cmd_smm_info_buffer {
  80         struct mbox_buffer_header header;
  81         struct smm_req_buffer req;
  82 } __packed __aligned(32);
  83
  84 /* MBOX_BIOS_CMD_SX_INFO */
  85 struct mbox_cmd_sx_info_buffer {
  86         struct mbox_buffer_header header;
  87         uint8_t sleep_type;
  88 } __packed __aligned(32);
  89
  90 /* MBOX_BIOS_CMD_PSP_FTPM_QUERY, MBOX_BIOS_CMD_PSP_CAPS_QUERY */
  91 struct mbox_cmd_capability_query_buffer {
  92         struct mbox_buffer_header header;
  93         uint32_t capabilities;
  94 } __packed __aligned(32);
  95
  96 /* MBOX_BIOS_CMD_HSTI_QUERY */
  97 struct mbox_cmd_hsti_query_buffer {
  98         struct mbox_buffer_header header;
  99         uint32_t state;
 100 } __packed __aligned(32);
 101
 102 /* MBOX_BIOS_CMD_SET_RPMC_ADDRESS */
 103 struct mbox_cmd_set_rpmc_address_buffer {
 104         struct mbox_buffer_header header;
 105         uint32_t address;
 106 } __packed __aligned(32);
 107
 108 /* MBOX_BIOS_CMD_SET_SPL_FUSE */
 109 struct mbox_cmd_late_spl_buffer {
 110         struct mbox_buffer_header header;
 111         uint32_t        spl_value;
 112 } __packed __aligned(32);
 113
 114 struct dtpm_config {
 115         uint32_t gpio;
 116 } __packed;
 117
 118 enum dtpm_request_type {
 119         DTPM_REQUEST_ACQUIRE,   /* Acquire I2C bus */
 120         DTPM_REQUEST_RELEASE,   /* Release I2C bus */
 121         DTPM_REQUEST_CONFIG,    /* Provide DTPM info */
 122         DTPM_REQUEST_MAX,
 123 };
 124
 125 /* MBOX_BIOS_CMD_I2C_TPM_ARBITRATION */
 126 struct mbox_cmd_dtpm_config_buffer {
 127         struct mbox_buffer_header header;
 128         uint32_t request_type;
 129         struct dtpm_config config;
 130 } __packed __aligned(32);
 131
 132 #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */
 133 #define PSP_CMD_TIMEOUT 1000 /* 1 second */
 134
 135 #define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */
 136 #define P2C_BUFFER_MAXSIZE 0x1000 /* PSP-to-core buffer */
 137
 138 /* PSP to x86 status */
 139 enum mbox_p2c_status {
 140         MBOX_PSP_SUCCESS                = 0x00,
 141         MBOX_PSP_INVALID_PARAMETER      = 0x01,
 142         MBOX_PSP_CRC_ERROR              = 0x02,
 143         MBOX_PSP_COMMAND_PROCESS_ERROR  = 0x04,
 144         MBOX_PSP_UNSUPPORTED            = 0x08,
 145         MBOX_PSP_SPI_BUSY_ASYNC         = 0x0a,
 146         MBOX_PSP_SPI_BUSY               = 0x0b,
 147 };
 148
 149 uintptr_t get_psp_mmio_base(void);
 150
 151 void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header);
 152
 153 /* This command needs to be implemented by the generation specific code. */
 154 int send_psp_command(uint32_t command, void *buffer);
 155
 156 enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities);
 157 enum cb_err psp_get_psp_capabilities(uint32_t *capabilities);
 158 enum cb_err psp_get_hsti_state(uint32_t *state);
 159 enum cb_err soc_read_c2p38(uint32_t *msg_38_value);
 160
 161 void enable_psp_smi(void);
 162
 163 #endif /* __AMD_PSP_DEF_H__ */