mb/google/nissa/var/rull: Configure Acoustic noise mitigation
[coreboot2.git] / src / soc / amd / common / block / spi / fch_spi.c
blobd9708b1eb06223671d62fe5096d2a29599dcd6a3
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/chip.h>
4 #include <amdblocks/lpc.h>
5 #include <amdblocks/psp_efs.h>
6 #include <amdblocks/spi.h>
7 #include <console/console.h>
8 #include <device/mmio.h>
9 #include <soc/iomap.h>
10 #include <soc/lpc.h>
11 #include <stdint.h>
13 static const char *spi_speed_str[8] = {
14 "66.66 Mhz",
15 "33.33 MHz",
16 "22.22 MHz",
17 "16.66 MHz",
18 "100 MHz",
19 "800 KHz",
20 "Invalid",
21 "Invalid"
24 static const char *read_mode_str[8] = {
25 "Normal Read (up to 33M)",
26 "Reserved",
27 "Dual IO (1-1-2)",
28 "Quad IO (1-1-4)",
29 "Dual IO (1-2-2)",
30 "Quad IO (1-4-4)",
31 "Normal Read (up to 66M)",
32 "Fast Read"
35 void show_spi_speeds_and_modes(void)
37 uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG);
38 uint32_t val32 = spi_read32(SPI_CNTRL0);
40 printk(BIOS_DEBUG, "SPI normal read speed: %s\n",
41 spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]);
42 printk(BIOS_DEBUG, "SPI fast read speed: %s\n",
43 spi_speed_str[DECODE_SPI_FAST_SPEED(val16)]);
44 printk(BIOS_DEBUG, "SPI alt read speed: %s\n",
45 spi_speed_str[DECODE_SPI_ALT_SPEED(val16)]);
46 printk(BIOS_DEBUG, "SPI TPM read speed: %s\n",
47 spi_speed_str[DECODE_SPI_TPM_SPEED(val16)]);
48 printk(BIOS_DEBUG, "SPI100: %s\n",
49 spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled");
50 printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]);
53 void __weak mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode)
55 /* No overriding SPI speeds. */
58 static uint8_t lower_speed(uint8_t speed1, uint8_t speed2)
60 uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M,
61 SPI_SPEED_33M, SPI_SPEED_66M, SPI_SPEED_100M};
63 for (int i = 0; i < ARRAY_SIZE(speeds); i++) {
64 if (speed1 == speeds[i])
65 return speed1;
66 if (speed2 == speeds[i])
67 return speed2;
70 /* Fall back to 16MHz if we got invalid speed values */
71 return SPI_SPEED_16M;
74 static void fch_spi_set_spi100(uint8_t norm, uint8_t fast, uint8_t alt, uint8_t tpm)
76 spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm));
77 spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE));
80 static void fch_spi_configure_4dw_burst(void)
82 uint16_t val = spi_read16(SPI100_HOST_PREF_CONFIG);
84 if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST))
85 val |= SPI_RD4DW_EN_HOST;
86 else
87 val &= ~SPI_RD4DW_EN_HOST;
89 spi_write16(SPI100_HOST_PREF_CONFIG, val);
92 static void fch_spi_set_read_mode(u32 mode)
94 uint32_t val = spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK;
96 spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode));
99 void fch_spi_config_modes(void)
101 uint8_t read_mode, fast_speed;
102 uint8_t normal_speed = CONFIG_NORMAL_READ_SPI_SPEED;
103 uint8_t alt_speed = CONFIG_ALT_SPI_SPEED;
104 uint8_t tpm_speed = CONFIG_TPM_SPI_SPEED;
106 if (!read_efs_spi_settings(&read_mode, &fast_speed)) {
107 read_mode = CONFIG_EFS_SPI_READ_MODE;
108 fast_speed = CONFIG_EFS_SPI_SPEED;
110 mainboard_spi_cfg_override(&fast_speed, &read_mode);
112 if (fast_speed != CONFIG_EFS_SPI_SPEED) {
113 normal_speed = lower_speed(normal_speed, fast_speed);
114 tpm_speed = lower_speed(tpm_speed, fast_speed);
115 alt_speed = lower_speed(alt_speed, fast_speed);
118 fch_spi_set_read_mode((u32)read_mode);
119 fch_spi_set_spi100(normal_speed, fast_speed, alt_speed, tpm_speed);
122 void fch_spi_early_init(void)
124 lpc_enable_spi_rom(SPI_ROM_ENABLE);
125 lpc_enable_spi_prefetch();
126 fch_spi_configure_4dw_burst();
127 fch_spi_config_modes();