soc/intel/pantherlake: Add core scaling factors read support
[coreboot2.git] / src / soc / amd / genoa_poc / Makefile.mk
blobbde8b1843f9989efd061b5743aa1ec97d566f5ad
1 ## SPDX-License-Identifier: GPL-2.0-only
2 ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y)
4 all-y += mmap_boot.c
5 all-y += reset.c
6 all-y += config.c
7 all-y += gpio.c
8 all-y += i2c.c
9 all-y += uart.c
11 bootblock-y += early_fch.c
12 bootblock-y += aoac.c
14 ramstage-y += acpi.c
15 ramstage-y += aoac.c
16 ramstage-y += chip.c
17 ramstage-y += cpu.c
18 ramstage-y += domain.c
19 ramstage-y += fch.c
20 ramstage-y += root_complex.c
21 ramstage-y += smihandler.c
22 ramstage-y += mca.c
24 smm-y += root_complex.c
25 smm-y += smihandler.c
26 smm-$(CONFIG_DEBUG_SMI) += uart.c
28 CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/acpi
29 CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/include
31 ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
32 CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
33 endif
36 # PSP Directory Table items
38 # Certain ordering requirements apply, however these are ensured by amdfwtool.
39 # For more information see "AMD Platform Security Processor BIOS Implementation
40 # Guide for Server EPYC Processors" #57299
43 FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
45 ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
46 PSP_SOFTFUSE_BITS += 7
47 endif
49 ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
50 # Enable secure debug unlock
51 PSP_SOFTFUSE_BITS += 0
52 OPT_TOKEN_UNLOCK="--token-unlock"
53 endif
55 # Use additional Soft Fuse bits specified in Kconfig
56 PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
58 # type = 0x3a
59 ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
60 PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
61 endif
63 # type = 0x55
64 SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
67 # BIOS Directory Table items - proper ordering is managed by amdfwtool
70 # type = 0x60
71 PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2)
73 # type = 0x61
74 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
76 # type = 0x62
77 PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
78 PSP_ELF_FILE=$(objcbfs)/bootblock.elf
79 PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
80 PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
82 # Helper function to return a value with given bit set
83 # Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
84 set-bit=$(call int-shift-left, 1 $(call _toint,$1))
85 PSP_SOFTFUSE=$(shell A=$(call int-add, \
86 $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A)
89 # Build the arguments to amdfwtool (order is unimportant). Missing file names
90 # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
93 add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
95 OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
96 $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \
97 $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
98 $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \
99 $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \
100 $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
102 OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
103 OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
104 OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
105 OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
107 OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
108 OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
109 OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
110 OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
112 OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
113 OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
115 AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
116 $(OPT_APOB_ADDR) \
117 $(OPT_DEBUG_AMDFWTOOL) \
118 $(OPT_PSP_BIOSBIN_FILE) \
119 $(OPT_PSP_BIOSBIN_DEST) \
120 $(OPT_PSP_BIOSBIN_SIZE) \
121 $(OPT_PSP_SOFTFUSE) \
122 --use-pspsecureos \
123 $(OPT_TOKEN_UNLOCK) \
124 $(OPT_WHITELIST_FILE) \
125 $(OPT_SPL_TABLE_FILE) \
126 $(OPT_EFS_SPI_READ_MODE) \
127 $(OPT_EFS_SPI_SPEED) \
128 $(OPT_EFS_SPI_MICRON_FLAG) \
129 --config $(CONFIG_AMDFW_CONFIG_FILE) \
130 --flashsize 0x1000000
132 $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
133 $$(PSP_APCB_FILES) \
134 $(DEP_FILES) \
135 $(AMDFWTOOL) \
136 $(obj)/fmap_config.h \
137 $(objcbfs)/bootblock.elf # this target also creates the .map file
138 $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
139 rm -f $@
140 @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
141 $(AMDFWTOOL) \
142 $(AMDFW_COMMON_ARGS) \
143 --location $(CONFIG_AMD_FWM_POSITION) \
144 --multilevel \
145 --output $@
147 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
148 rm -f $@
149 @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
150 $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
151 --maxsize $(PSP_BIOSBIN_SIZE)
153 endif