soc/intel/pantherlake: Add core scaling factors read support
[coreboot2.git] / src / soc / amd / genoa_poc / chip.c
blob75f5bccb004e5d79baff43c1f4d449dba2ef46f8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/acpi.h>
4 #include <amdblocks/data_fabric.h>
5 #include <device/device.h>
6 #include <soc/southbridge.h>
7 #include <soc/southbridge.h>
8 #include <vendorcode/amd/opensil/opensil.h>
10 static void soc_init(void *chip_info)
12 default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
14 setup_opensil();
15 opensil_xSIM_timepoint_1();
17 data_fabric_print_mmio_conf();
19 fch_init(chip_info);
22 static void soc_final(void *chip_info)
26 struct chip_operations soc_amd_genoa_poc_ops = {
27 .name = "AMD Genoa SoC Proof of Concept",
28 .init = soc_init,
29 .final = soc_final,