src/soc/amd/genoa_poc/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __GENOA_POC_CHIP_H__
   4 #define __GENOA_POC_CHIP_H__
   5
   6 #include <amdblocks/chip.h>
   7 #include <amdblocks/i2c.h>
   8 #include <drivers/i2c/designware/dw_i2c.h>
   9 #include <soc/iomap.h>
  10 #include <types.h>
  11
  12 struct usb31_phy_settings {
  13         uint8_t rx_ana_iq_phase_adjust;
  14         uint8_t rx_eq_delta_iq_ovrd_en;
  15         uint8_t rx_eq_delta_iq_ovrd_val;
  16         uint8_t rx_iq_phase_adjust;
  17         uint8_t tx_vboost_lvl_en;
  18         uint8_t tx_vboost_lvl;
  19         uint8_t rx_vref_ctrl_en;
  20         uint8_t rx_vref_ctrl;
  21         uint8_t tx_vboost_lvl_en_x;
  22         uint8_t tx_vboost_lvl_x;
  23         uint8_t rx_vref_ctrl_en_x;
  24         uint8_t rx_vref_ctrl_x;
  25 };
  26
  27 struct soc_usb_config {
  28         uint8_t xhci0_enable : 1;
  29         uint8_t xhci1_enable : 1;
  30         struct {
  31                 uint8_t port0 : 4;
  32                 uint8_t port1 : 4;
  33                 uint8_t port2 : 4;
  34                 uint8_t port3 : 4;
  35                 uint8_t port4 : 4;
  36                 uint8_t port5 : 4;
  37                 uint8_t port6 : 4;
  38                 uint8_t port7 : 4;
  39         } usb2_oc_pins[2];
  40         struct {
  41                 uint8_t port0 : 4;
  42                 uint8_t port1 : 4;
  43                 uint8_t port2 : 4;
  44                 uint8_t port3 : 4;
  45         }  usb3_oc_pins[2];
  46         bool polarity_cfg_low;
  47         union {
  48                 struct {
  49                         uint8_t port0 : 2;
  50                         uint8_t port1 : 2;
  51                         uint8_t port2 : 2; /* Broken in OpenSIL */
  52                         uint8_t port3 : 2; /* Broken in OpenSIL */
  53                 };
  54                 uint8_t raw;
  55         } usb3_force_gen1;
  56         bool usb31_phy_enable;
  57         struct usb31_phy_settings usb31_phy[8];
  58         bool s1_usb31_phy_enable;
  59         struct usb31_phy_settings s1_usb31_phy[8];
  60 };
  61
  62 struct soc_amd_genoa_poc_config {
  63         struct soc_amd_common_config common_config;
  64
  65         u8 i2c_scl_reset;
  66         struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
  67
  68         struct soc_usb_config usb;
  69 };
  70
  71 #endif /* __GENOA_POC_CHIP_H__ */