src/soc/amd/genoa_poc/fch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <amdblocks/acpimmio.h>
   5 #include <amdblocks/amd_pci_util.h>
   6 #include <amdblocks/gpio.h>
   7 #include <amdblocks/smi.h>
   8 #include <cpu/x86/smm.h>
   9 #include <soc/amd_pci_int_defs.h>
  10 #include <soc/smi.h>
  11 #include <soc/southbridge.h>
  12
  13 /*
  14  * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
  15  * provides a visible association with the index, therefore helping
  16  * maintainability of table. If a new index/name is defined in
  17  * amd_pci_int_defs.h, just add the pair at the end of this table.
  18  * Order is not important.
  19  */
  20 static const struct irq_idx_name irq_association[] = {
  21         { PIRQ_A,       "INTA#" },
  22         { PIRQ_B,       "INTB#" },
  23         { PIRQ_C,       "INTC#" },
  24         { PIRQ_D,       "INTD#" },
  25         { PIRQ_E,       "INTE#" },
  26         { PIRQ_F,       "INTF#/GENINT2" },
  27         { PIRQ_G,       "INTG#" },
  28         { PIRQ_H,       "INTH#" },
  29         { PIRQ_MISC,    "Misc" },
  30         { PIRQ_MISC0,   "Misc0" },
  31         { PIRQ_HPET_L,  "HPET_L" },
  32         { PIRQ_HPET_H,  "HPET_H" },
  33         { PIRQ_SIRQA,   "Ser IRQ INTA" },
  34         { PIRQ_SIRQB,   "Ser IRQ INTB" },
  35         { PIRQ_SIRQC,   "Ser IRQ INTC" },
  36         { PIRQ_SIRQD,   "Ser IRQ INTD" },
  37         { PIRQ_SCI,     "SCI" },
  38         { PIRQ_SMBUS,   "SMBUS" },
  39         { PIRQ_ASF,     "ASF" },
  40         { PIRQ_PMON,    "PerMon" },
  41         { PIRQ_SDIO,    "SDIO" },
  42         { PIRQ_GPP0,    "GPP0" },
  43         { PIRQ_GPP1,    "GPP1" },
  44         { PIRQ_GPP2,    "GPP2" },
  45         { PIRQ_GPP3,    "GPP3" },
  46         { PIRQ_GSCI,    "GEvent SCI" },
  47         { PIRQ_GSMI,    "GEvent SMI" },
  48         { PIRQ_GPIO,    "GPIO" },
  49         { PIRQ_I2C0,    "I2C0" },
  50         { PIRQ_I2C1,    "I2C1" },
  51         { PIRQ_I2C2,    "I2C2" },
  52         { PIRQ_I2C3,    "I2C3" },
  53         { PIRQ_UART0,   "UART0" },
  54         { PIRQ_UART1,   "UART1" },
  55         { PIRQ_I2C4,    "I2C4" },
  56         { PIRQ_I2C5,    "I2C5" },
  57         { PIRQ_UART2,   "UART2" },
  58         { PIRQ_UART3,   "UART3" },
  59 };
  60
  61 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
  62 {
  63         *size = ARRAY_SIZE(irq_association);
  64         return irq_association;
  65 }
  66
  67 static void set_pci_irqs(void)
  68 {
  69         /* Write PCI_INTR regs 0xC00/0xC01 */
  70         write_pci_int_table();
  71
  72         /* TODO: PIRQ configuration */
  73 }
  74
  75 static void fch_init_acpi_ports(void)
  76 {
  77         /* Configure and enable APMC SMI Command Port */
  78         pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
  79         configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
  80 }
  81
  82 void fch_init(void *chip_info)
  83 {
  84         set_pci_irqs();
  85         fch_init_acpi_ports();
  86 }