mb/google/rauru: Enable vcore DVFS in romstage
[coreboot2.git] / src / soc / amd / genoa_poc / i2c.c
blob6436e3d190e0e0b3f6b62b9154dec01f36097fb7
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/i2c.h>
4 #include <soc/i2c.h>
5 #include <soc/southbridge.h>
6 #include <static.h>
7 #include "chip.h"
9 /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
10 static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
11 I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
12 I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
13 I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
14 I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
15 I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL),
16 I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL),
19 static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
20 { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
21 { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
22 { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
23 { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
24 { I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" },
25 { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" }
28 void reset_i2c_peripherals(void)
30 const struct soc_amd_genoa_poc_config *cfg = config_of_soc();
31 struct soc_i2c_peripheral_reset_info reset_info;
33 reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
34 reset_info.i2c_scl = i2c_scl_pins;
35 reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
36 sb_reset_i2c_peripherals(&reset_info);
39 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
41 /* TODO: write I2C pad control registers */
44 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
46 *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
47 return i2c_ctrlr;
50 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
52 const struct soc_amd_genoa_poc_config *config = config_of_soc();
54 *num_buses = ARRAY_SIZE(config->i2c);
55 return config->i2c;