soc/intel/pantherlake: Add core scaling factors read support
[coreboot2.git] / src / soc / amd / genoa_poc / reset.c
blobac0c9817189ee1a0b853c1093a51e4daa880847f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/io.h>
4 #include <cf9_reset.h>
5 #include <reset.h>
6 #include <soc/southbridge.h>
7 #include <amdblocks/acpimmio.h>
8 #include <amdblocks/reset.h>
10 void do_cold_reset(void)
12 /* De-assert and then assert all PwrGood signals on CF9 reset. */
13 pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
14 TOGGLE_ALL_PWR_GOOD);
15 outb(RST_CPU | SYS_RST, RST_CNT);
18 void do_warm_reset(void)
20 /* Warm resets are not supported and must be executed as cold */
21 do_cold_reset();
24 void do_board_reset(void)
26 do_cold_reset();