src/soc/amd/genoa_poc/root_complex.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/ioapic.h>
   4 #include <amdblocks/root_complex.h>
   5 #include <types.h>
   6
   7 static const struct domain_iohc_info iohc_info[] = {
   8         [0] = {
   9                 .fabric_id = 0x22,
  10                 .misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
  11         },
  12         [1] = {
  13                 .fabric_id = 0x23,
  14                 .misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
  15         },
  16         [2] = {
  17                 .fabric_id = 0x21,
  18                 .misc_smn_base = SMN_IOHC_MISC_BASE_13E1,
  19         },
  20         [3] = {
  21                 .fabric_id = 0x20,
  22                 .misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
  23         },
  24 };
  25
  26 const struct domain_iohc_info *get_iohc_info(size_t *count)
  27 {
  28         *count = ARRAY_SIZE(iohc_info);
  29         return iohc_info;
  30 }
  31
  32 static const struct non_pci_mmio_reg non_pci_mmio[] = {
  33         { 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  34         { 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  35         { 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  36         /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
  37            tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
  38            resource. */
  39         { 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
  40         { 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  41         { 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  42         { 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
  43         { 0x310, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
  44         { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
  45 };
  46
  47 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
  48 {
  49         *count = ARRAY_SIZE(non_pci_mmio);
  50         return non_pci_mmio;
  51 }