src/soc/amd/glinda/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Update for Glinda */
   4
   5 #ifndef GLINDA_CHIP_H
   6 #define GLINDA_CHIP_H
   7
   8 #include <amdblocks/chip.h>
   9 #include <amdblocks/i2c.h>
  10 #include <amdblocks/pci_clk_req.h>
  11 #include <gpio.h>
  12 #include <soc/i2c.h>
  13 #include <soc/southbridge.h>
  14 #include <drivers/i2c/designware/dw_i2c.h>
  15 #include <types.h>
  16 #include <vendorcode/amd/fsp/glinda/FspUsb.h>
  17
  18 struct soc_amd_glinda_config {
  19         struct soc_amd_common_config common_config;
  20         u8 i2c_scl_reset;
  21         struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
  22         struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
  23
  24         /* Enable S0iX support */
  25         bool s0ix_enable;
  26
  27         enum {
  28                 DOWNCORE_AUTO = 0,
  29                 DOWNCORE_1 = 1, /* Run with 1 physical core */
  30                 DOWNCORE_2 = 3, /* Run with 2 physical cores */
  31                 DOWNCORE_3 = 4, /* Run with 3 physical cores */
  32                 DOWNCORE_4 = 6, /* Run with 4 physical cores */
  33                 DOWNCORE_5 = 8, /* Run with 5 physical cores */
  34                 DOWNCORE_6 = 9, /* Run with 6 physical cores */
  35                 DOWNCORE_7 = 10, /* Run with 7 physical cores */
  36         } downcore_mode;
  37         bool disable_smt; /* disable second thread on all physical cores */
  38
  39         uint8_t stt_control;
  40         uint8_t stt_pcb_sensor_count;
  41         uint16_t stt_min_limit;
  42         uint16_t stt_m1;
  43         uint16_t stt_m2;
  44         uint16_t stt_m3;
  45         uint16_t stt_m4;
  46         uint16_t stt_m5;
  47         uint16_t stt_m6;
  48         uint16_t stt_c_apu;
  49         uint16_t stt_c_gpu;
  50         uint16_t stt_c_hs2;
  51         uint16_t stt_alpha_apu;
  52         uint16_t stt_alpha_gpu;
  53         uint16_t stt_alpha_hs2;
  54         uint16_t stt_skin_temp_apu;
  55         uint16_t stt_skin_temp_gpu;
  56         uint16_t stt_skin_temp_hs2;
  57         uint16_t stt_error_coeff;
  58         uint16_t stt_error_rate_coefficient;
  59
  60         /* Default */
  61         uint8_t stapm_boost;
  62         uint32_t stapm_time_constant_s;
  63         uint32_t apu_only_sppt_limit;
  64         uint32_t sustained_power_limit_mW;
  65         uint32_t fast_ppt_limit_mW;
  66         uint32_t slow_ppt_limit_mW;
  67         uint32_t slow_ppt_time_constant_s;
  68         uint32_t thermctl_limit_degreeC;
  69         uint32_t vrm_current_limit_mA;
  70         uint32_t vrm_maximum_current_limit_mA;
  71         uint32_t vrm_soc_current_limit_mA;
  72         /* Throttle (e.g., Low/No Battery) */
  73         uint32_t vrm_current_limit_throttle_mA;
  74         uint32_t vrm_maximum_current_limit_throttle_mA;
  75         uint32_t vrm_soc_current_limit_throttle_mA;
  76
  77         uint8_t smartshift_enable;
  78
  79         uint8_t system_configuration;
  80
  81         uint8_t cppc_ctrl;
  82         uint8_t cppc_perf_limit_max_range;
  83         uint8_t cppc_perf_limit_min_range;
  84         uint8_t cppc_epp_max_range;
  85         uint8_t cppc_epp_min_range;
  86         uint8_t cppc_preferred_cores;
  87
  88         /* telemetry settings */
  89         uint32_t telemetry_vddcrvddfull_scale_current_mA;
  90         uint32_t telemetry_vddcrvddoffset;
  91         uint32_t telemetry_vddcrsocfull_scale_current_mA;
  92         uint32_t telemetry_vddcrsocoffset;
  93
  94         /* The array index is the general purpose PCIe clock output number. Values in here
  95            aren't the values written to the register to have the default to be always on. */
  96         enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
  97
  98         /* performance policy for the PCIe links: power consumption vs. link speed */
  99         enum {
 100                 DXIO_PSPP_DISABLED = 0,
 101                 DXIO_PSPP_PERFORMANCE,
 102                 DXIO_PSPP_BALANCED,
 103                 DXIO_PSPP_POWERSAVE,
 104         } pspp_policy;
 105
 106         uint8_t usb_phy_custom;
 107         struct usb_phy_config usb_phy;
 108 };
 109
 110 #endif /* GLINDA_CHIP_H */