soc/intel/pantherlake: Add core scaling factors read support
[coreboot2.git] / src / soc / amd / glinda / espi_util.c
blob067a722e4127e3ce39877f86d9b273804548f4d8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/spi.h>
4 #include <soc/espi.h>
5 #include <types.h>
7 #define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */
8 #define LOCK_SPIX10_BIT2 BIT(3)
9 #define ESPI_MUX_SPI1 BIT(2)
10 #define ROM_ADDR_WR_PROT BIT(1)
12 void espi_switch_to_spi1_pads(void)
14 uint8_t reg = spi_read8(ESPI_CNTRL_REGISTER);
16 reg |= ESPI_MUX_SPI1;
18 spi_write8(ESPI_CNTRL_REGISTER, reg);