src/soc/amd/glinda/uart.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Update for Glinda */
   4
   5 #include <amdblocks/gpio.h>
   6 #include <amdblocks/uart.h>
   7 #include <commonlib/helpers.h>
   8 #include <device/mmio.h>
   9 #include <gpio.h>
  10 #include <soc/aoac_defs.h>
  11 #include <soc/iomap.h>
  12 #include <soc/southbridge.h>
  13 #include <soc/uart.h>
  14 #include <types.h>
  15
  16 static const struct soc_uart_ctrlr_info uart_info[] = {
  17         [0] =   { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", {
  18                         PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
  19                         PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
  20                 } },
  21         [1] =   { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", {
  22                         PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
  23                         PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
  24                 } },
  25         [2] =   { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", {
  26                         PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
  27                         PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
  28                 } },
  29         [3] =   { APU_UART3_BASE, FCH_AOAC_DEV_UART3, "FUR3", {
  30                         PAD_NF(GPIO_135, UART3_TXD, PULL_NONE),
  31                         PAD_NF(GPIO_137, UART3_RXD, PULL_NONE),
  32                 } },
  33         [4] =   { APU_UART4_BASE, FCH_AOAC_DEV_UART4, "FUR4", {
  34                         PAD_NF(GPIO_156, UART4_TXD, PULL_NONE),
  35                         PAD_NF(GPIO_155, UART4_RXD, PULL_NONE),
  36                 } },
  37 };
  38
  39 const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
  40 {
  41         *num_ctrlrs = ARRAY_SIZE(uart_info);
  42         return uart_info;
  43 }
  44
  45 void clear_uart_legacy_config(void)
  46 {
  47         write16p(FCH_LEGACY_UART_DECODE, 0);
  48 }