mb/google/rauru: Enable vcore DVFS in romstage
[coreboot2.git] / src / soc / amd / glinda / xhci.c
blob70a0d84864177b4db6a7e8acef59b16edefe10df
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* TODO: Update for Glinda */
5 #include <amdblocks/gpio.h>
6 #include <amdblocks/smi.h>
7 #include <bootstate.h>
8 #include <device/device.h>
9 #include <device/pci_ids.h>
10 #include <drivers/usb/pci_xhci/pci_xhci.h>
11 #include <soc/pci_devs.h>
12 #include <soc/smi.h>
14 static const struct sci_source xhci_sci_sources[] = {
16 .scimap = SMITYPE_XHC0_PME,
17 .gpe = GEVENT_31,
18 .direction = SMI_SCI_LVL_HIGH,
19 .level = SMI_SCI_EDG
22 .scimap = SMITYPE_XHC1_PME,
23 .gpe = GEVENT_31,
24 .direction = SMI_SCI_LVL_HIGH,
25 .level = SMI_SCI_EDG
28 .scimap = SMITYPE_XHC3_PME,
29 .gpe = GEVENT_31,
30 .direction = SMI_SCI_LVL_HIGH,
31 .level = SMI_SCI_EDG
34 .scimap = SMITYPE_XHC4_PME,
35 .gpe = GEVENT_31,
36 .direction = SMI_SCI_LVL_HIGH,
37 .level = SMI_SCI_EDG
41 enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
43 if (dev->upstream->dev->path.type != DEVICE_PATH_PCI)
44 return CB_ERR_ARG;
46 if (dev->path.type != DEVICE_PATH_PCI)
47 return CB_ERR_ARG;
49 if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
50 if (dev->path.pci.devfn == XHCI1_DEVFN) {
51 *gpe = xhci_sci_sources[1].gpe;
52 return CB_SUCCESS;
54 } else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
55 if (dev->path.pci.devfn == XHCI0_DEVFN) {
56 *gpe = xhci_sci_sources[0].gpe;
57 return CB_SUCCESS;
58 } else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) {
59 *gpe = xhci_sci_sources[2].gpe;
60 return CB_SUCCESS;
61 } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) {
62 *gpe = xhci_sci_sources[3].gpe;
63 return CB_SUCCESS;
67 return CB_ERR_ARG;
70 static void configure_xhci_sci(void *unused)
72 gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);
75 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);