src/soc/amd/mendocino/root_complex.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Check if this is still correct */
   4
   5 #include <acpi/acpigen.h>
   6 #include <amdblocks/alib.h>
   7 #include <amdblocks/data_fabric.h>
   8 #include <amdblocks/ioapic.h>
   9 #include <amdblocks/root_complex.h>
  10 #include <arch/ioapic.h>
  11 #include <device/device.h>
  12 #include <device/pci.h>
  13 #include <fsp/amd_misc_data.h>
  14 #include <soc/iomap.h>
  15 #include <static.h>
  16 #include <stdint.h>
  17 #include "chip.h"
  18
  19 #define TDP_15W 15
  20 #define DPTC_TOTAL_UPDATE_PARAMS        13
  21
  22 struct dptc_input {
  23         uint16_t size;
  24         struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
  25 } __packed;
  26
  27
  28 #define DPTC_INPUTS(_thermctllmit, _spptTimeConst, _fast, _slow,        \
  29         _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit,     \
  30         _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttAlphaApu, _sttSkinTempLimitApu)     \
  31         {                                                                       \
  32                 .size = sizeof(struct dptc_input),                              \
  33                 .params = {                                                     \
  34                         {                                                       \
  35                                 .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID,       \
  36                                 .value = _thermctllmit,                         \
  37                         },                                                      \
  38                         {                                                       \
  39                                 .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID,      \
  40                                 .value = _spptTimeConst,                        \
  41                         },                                                      \
  42                         {                                                       \
  43                                 .id = ALIB_DPTC_FAST_PPT_LIMIT_ID,              \
  44                                 .value = _fast,                                 \
  45                         },                                                      \
  46                         {                                                       \
  47                                 .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID,              \
  48                                 .value = _slow,                                 \
  49                         },                                                      \
  50                         {                                                       \
  51                                 .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID,           \
  52                                 .value = _vrmCurrentLimit,                      \
  53                         },                                                      \
  54                         {                                                       \
  55                                 .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT,      \
  56                                 .value = _vrmMaxCurrentLimit,                   \
  57                         },                                                      \
  58                         {                                                       \
  59                                 .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID,       \
  60                                 .value = _vrmSocCurrentLimit,                   \
  61                         },                                                      \
  62                         {                                                       \
  63                                 .id = ALIB_DPTC_STT_MIN_LIMIT_ID,               \
  64                                 .value = _sttMinLimit,                          \
  65                         },                                                      \
  66                         {                                                       \
  67                                 .id = ALIB_DPTC_STT_M1_ID,                      \
  68                                 .value = _sttM1,                                \
  69                         },                                                      \
  70                         {                                                       \
  71                                 .id = ALIB_DPTC_STT_M2_ID,                      \
  72                                 .value = _sttM2,                                \
  73                         },                                                      \
  74                         {                                                       \
  75                                 .id = ALIB_DPTC_STT_C_APU_ID,                   \
  76                                 .value = _sttCApu,                              \
  77                         },                                                      \
  78                         {                                                       \
  79                                 .id = ALIB_DPTC_STT_ALPHA_APU,                  \
  80                                 .value = _sttAlphaApu,                          \
  81                         },                                                      \
  82                         {                                                       \
  83                                 .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID,      \
  84                                 .value = _sttSkinTempLimitApu,                  \
  85                         },                                                      \
  86                 },                                                              \
  87         }
  88
  89 static void acipgen_dptci(void)
  90 {
  91         const struct soc_amd_mendocino_config *config = config_of_soc();
  92
  93         /* Normal mode DPTC values. */
  94         struct dptc_input default_input = DPTC_INPUTS(
  95                 config->thermctl_limit_degreeC,
  96                 config->slow_ppt_time_constant_s,
  97                 config->fast_ppt_limit_mW,
  98                 config->slow_ppt_limit_mW,
  99                 config->vrm_current_limit_mA,
 100                 config->vrm_maximum_current_limit_mA,
 101                 config->vrm_soc_current_limit_mA,
 102                 config->stt_min_limit,
 103                 config->stt_m1,
 104                 config->stt_m2,
 105                 config->stt_c_apu,
 106                 config->stt_alpha_apu,
 107                 config->stt_skin_temp_apu);
 108         acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
 109
 110         /* Low/No Battery */
 111         struct dptc_input no_battery_input = DPTC_INPUTS(
 112                 config->thermctl_limit_degreeC,
 113                 config->slow_ppt_time_constant_s,
 114                 config->fast_ppt_limit_mW,
 115                 config->slow_ppt_limit_mW,
 116                 config->vrm_current_limit_throttle_mA,
 117                 config->vrm_maximum_current_limit_throttle_mA,
 118                 config->vrm_soc_current_limit_throttle_mA,
 119                 config->stt_min_limit,
 120                 config->stt_m1,
 121                 config->stt_m2,
 122                 config->stt_c_apu,
 123                 config->stt_alpha_apu,
 124                 config->stt_skin_temp_apu);
 125         acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input,
 126                 sizeof(no_battery_input));
 127
 128 #if (CONFIG(FEATURE_TABLET_MODE_DPTC))
 129         struct dptc_input tablet_input = DPTC_INPUTS(
 130                 config->thermctl_limit_degreeC,
 131                 config->slow_ppt_time_constant_s,
 132                 config->fast_ppt_limit_mW,
 133                 config->slow_ppt_limit_mW,
 134                 config->vrm_current_limit_mA,
 135                 config->vrm_maximum_current_limit_mA,
 136                 config->vrm_soc_current_limit_mA,
 137                 config->stt_min_limit,
 138                 config->stt_m1_tablet,
 139                 config->stt_m2_tablet,
 140                 config->stt_c_apu_tablet,
 141                 config->stt_alpha_apu_tablet,
 142                 config->stt_skin_temp_apu);
 143         acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input));
 144 #endif
 145
 146 #if (CONFIG(FEATURE_DYNAMIC_DPTC))
 147         /* Profile B */
 148         struct dptc_input thermal_B_input = DPTC_INPUTS(
 149                 config->thermctl_limit_degreeC,
 150                 config->slow_ppt_time_constant_s_B,
 151                 config->fast_ppt_limit_mW_B,
 152                 config->slow_ppt_limit_mW_B,
 153                 config->vrm_current_limit_throttle_mA,
 154                 config->vrm_maximum_current_limit_mA,
 155                 config->vrm_soc_current_limit_mA,
 156                 config->stt_min_limit_B,
 157                 config->stt_m1_B,
 158                 config->stt_m2_B,
 159                 config->stt_c_apu_B,
 160                 config->stt_alpha_apu,
 161                 config->stt_skin_temp_apu_B);
 162         acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input,
 163                 sizeof(thermal_B_input));
 164
 165         /* Profile C */
 166         struct dptc_input thermal_C_input = DPTC_INPUTS(
 167                 config->thermctl_limit_degreeC,
 168                 config->slow_ppt_time_constant_s_C,
 169                 config->fast_ppt_limit_mW_C,
 170                 config->slow_ppt_limit_mW_C,
 171                 config->vrm_current_limit_mA,
 172                 config->vrm_maximum_current_limit_mA,
 173                 config->vrm_soc_current_limit_mA,
 174                 config->stt_min_limit_C,
 175                 config->stt_m1_C,
 176                 config->stt_m2_C,
 177                 config->stt_c_apu_C,
 178                 config->stt_alpha_apu,
 179                 config->stt_skin_temp_apu_C);
 180         acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input,
 181                 sizeof(thermal_C_input));
 182
 183         /* Profile D */
 184         struct dptc_input thermal_D_input = DPTC_INPUTS(
 185                 config->thermctl_limit_degreeC,
 186                 config->slow_ppt_time_constant_s_D,
 187                 config->fast_ppt_limit_mW_D,
 188                 config->slow_ppt_limit_mW_D,
 189                 config->vrm_current_limit_mA,
 190                 config->vrm_maximum_current_limit_mA,
 191                 config->vrm_soc_current_limit_mA,
 192                 config->stt_min_limit_D,
 193                 config->stt_m1_D,
 194                 config->stt_m2_D,
 195                 config->stt_c_apu_D,
 196                 config->stt_alpha_apu,
 197                 config->stt_skin_temp_apu_D);
 198         acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input,
 199                 sizeof(thermal_D_input));
 200
 201         /* Profile E */
 202         struct dptc_input thermal_E_input = DPTC_INPUTS(
 203                 config->thermctl_limit_degreeC,
 204                 config->slow_ppt_time_constant_s_E,
 205                 config->fast_ppt_limit_mW_E,
 206                 config->slow_ppt_limit_mW_E,
 207                 config->vrm_current_limit_mA,
 208                 config->vrm_maximum_current_limit_mA,
 209                 config->vrm_soc_current_limit_mA,
 210                 config->stt_min_limit_E,
 211                 config->stt_m1_E,
 212                 config->stt_m2_E,
 213                 config->stt_c_apu_E,
 214                 config->stt_alpha_apu,
 215                 config->stt_skin_temp_apu_E);
 216         acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input,
 217                 sizeof(thermal_E_input));
 218
 219         /* Profile F */
 220         struct dptc_input thermal_F_input = DPTC_INPUTS(
 221                 config->thermctl_limit_degreeC,
 222                 config->slow_ppt_time_constant_s_F,
 223                 config->fast_ppt_limit_mW_F,
 224                 config->slow_ppt_limit_mW_F,
 225                 config->vrm_current_limit_mA,
 226                 config->vrm_maximum_current_limit_mA,
 227                 config->vrm_soc_current_limit_mA,
 228                 config->stt_min_limit_F,
 229                 config->stt_m1_F,
 230                 config->stt_m2_F,
 231                 config->stt_c_apu_F,
 232                 config->stt_alpha_apu,
 233                 config->stt_skin_temp_apu_F);
 234         acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input,
 235                 sizeof(thermal_F_input));
 236 #endif
 237 }
 238
 239 static void root_complex_fill_ssdt(const struct device *device)
 240 {
 241         uint32_t tdp = 0;
 242
 243         if (get_amd_smu_reported_tdp(&tdp) != CB_SUCCESS) {
 244                 /* Unknown TDP, so return rather than setting invalid values. */
 245                 return;
 246         }
 247         /* TODO(b/249359574): Add support for 6W DPTC values. */
 248         if (tdp != TDP_15W)
 249                 return;
 250
 251         if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 252                 acipgen_dptci();
 253 }
 254
 255 static const char *gnb_acpi_name(const struct device *dev)
 256 {
 257         return "GNB";
 258 }
 259
 260 struct device_operations mendocino_root_complex_operations = {
 261         /* The root complex has no PCI BARs implemented, so there's no need to call
 262            pci_dev_read_resources for it */
 263         .read_resources         = noop_read_resources,
 264         .set_resources          = noop_set_resources,
 265         .enable_resources       = pci_dev_enable_resources,
 266         .acpi_name              = gnb_acpi_name,
 267         .acpi_fill_ssdt         = root_complex_fill_ssdt,
 268 };
 269
 270 static const struct domain_iohc_info iohc_info[] = {
 271         [0] = {
 272                 .fabric_id = IOMS0_FABRIC_ID,
 273                 .misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
 274         },
 275 };
 276
 277 const struct domain_iohc_info *get_iohc_info(size_t *count)
 278 {
 279         *count = ARRAY_SIZE(iohc_info);
 280         return iohc_info;
 281 }
 282
 283 static const struct non_pci_mmio_reg non_pci_mmio[] = {
 284         { 0x2d8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 285         { 0x2e0, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 286         { 0x2e8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 287         /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
 288            tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
 289            resource. */
 290         { 0x2f0, 0xffffffffff00ull,   4 * KiB, IOMMU_IOAPIC_IDX },
 291         { 0x2f8, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 292         { 0x300, 0xfffffff00000ull,   1 * MiB, NON_PCI_RES_IDX_AUTO },
 293         { 0x308, 0xfffffffff000ull,   4 * KiB, NON_PCI_RES_IDX_AUTO },
 294         { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
 295 };
 296
 297 const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
 298 {
 299         *count = ARRAY_SIZE(non_pci_mmio);
 300         return non_pci_mmio;
 301 }