soc/amd/common/psp/psp_def.h: increase P2C_BUFFER_MAXSIZE
[coreboot2.git] / src / soc / amd / phoenix / acpi.c
bloba182dfbb129c0ee06e6d3996a994abd07706cd53
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* TODO: Update for Phoenix */
4 /* TODO: See what can be made common */
6 /* ACPI - create the Fixed ACPI Description Tables (FADT) */
8 #include <acpi/acpi.h>
9 #include <acpi/acpigen.h>
10 #include <amdblocks/acpi.h>
11 #include <amdblocks/cppc.h>
12 #include <amdblocks/cpu.h>
13 #include <amdblocks/acpimmio.h>
14 #include <amdblocks/ioapic.h>
15 #include <arch/ioapic.h>
16 #include <arch/smp/mpspec.h>
17 #include <console/console.h>
18 #include <cpu/amd/cpuid.h>
19 #include <device/device.h>
20 #include <soc/iomap.h>
21 #include <static.h>
22 #include <types.h>
23 #include <vendorcode/amd/opensil/opensil.h>
24 #include "chip.h"
27 * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
28 * in the ACPI 3.0b specification.
30 void acpi_fill_fadt(acpi_fadt_t *fadt)
32 const struct soc_amd_phoenix_config *cfg = config_of_soc();
34 if (CONFIG(PLATFORM_USES_FSP2_0)) {
35 printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
37 fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
38 fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
39 fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
40 fadt->gpe0_blk = ACPI_GPE0_BLK;
41 } else {
42 /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
43 opensil_fill_fadt_io_ports(fadt);
46 fadt->pm1_evt_len = 4; /* 32 bits */
47 fadt->pm1_cnt_len = 2; /* 16 bits */
48 fadt->pm_tmr_len = 4; /* 32 bits */
49 fadt->gpe0_blk_len = 8; /* 64 bits */
51 fill_fadt_extended_pm_io(fadt);
53 fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
54 fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
55 ACPI_FADT_C1_SUPPORTED |
56 ACPI_FADT_S4_RTC_WAKE |
57 ACPI_FADT_32BIT_TIMER |
58 ACPI_FADT_PCI_EXPRESS_WAKE |
59 ACPI_FADT_PLATFORM_CLOCK |
60 ACPI_FADT_S4_RTC_VALID |
61 ACPI_FADT_REMOTE_POWER_ON;
62 if (cfg->s0ix_enable)
63 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
65 fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
68 unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
69 acpi_rsdp_t *rsdp)
71 /* IVRS */
72 current = acpi_add_ivrs_table(current, rsdp);
74 if (CONFIG(PLATFORM_USES_FSP2_0))
75 current = acpi_add_fsp_tables(current, rsdp);
76 else
77 current = acpi_add_opensil_tables(current, rsdp);
79 return current;
82 const acpi_cstate_t cstate_cfg_table[] = {
83 [0] = {
84 .ctype = 1,
85 .latency = 1,
86 .power = 0,
88 [1] = {
89 .ctype = 2,
90 .latency = 0x12,
91 .power = 0,
93 [2] = {
94 .ctype = 3,
95 .latency = 350,
96 .power = 0,
100 const acpi_cstate_t *get_cstate_config_data(size_t *size)
102 *size = ARRAY_SIZE(cstate_cfg_table);
103 return cstate_cfg_table;