src/soc/amd/phoenix/chip_opensil.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef PHOENIX_CHIP_OPENSIL_H
   4 #define PHOENIX_CHIP_OPENSIL_H
   5
   6 #include <types.h>
   7
   8 #define DDI_DESCRIPTOR_COUNT    5
   9
  10 /* DDI display connector type */
  11 enum ddi_connector_type {
  12         DDI_DP = 0,             // DP
  13         DDI_EDP,                // eDP
  14         DDI_SINGLE_LINK_DVI,    // Single Link DVI-D
  15         DDI_DUAL_LINK_DVI,      // Dual Link DVI-D
  16         DDI_HDMI,               // HDMI
  17         DDI_DP_TO_VGA,          // DP-to-VGA
  18         DDI_DP_TO_LVDS,         // DP-to-LVDS
  19         DDI_NUTMEG_DP_TO_VGA,   // Hudson-2 NutMeg DP-to-VGA
  20         DDI_SINGLE_LINK_DVI_I,  // Single Link DVI-I
  21         DDI_DP_W_TYPEC,         // DP with USB type C
  22         DDI_DP_WO_TYPEC,        // DP without USB type C
  23         DDI_EDP_TO_LVDS,        // eDP-to-LVDS translator chip without AMD SW init
  24         DDI_EDP_TO_LVDS_SW,     // eDP-to-LVDS translator which requires AMD SW init
  25         DDI_AUTO_DETECT,        // VBIOS auto detect connector type
  26         DDI_UNUSED_TYPE,        // UnusedType
  27         DDI_MAX_CONNECTOR_TYPE  // Not valid value, used to verify input
  28 };
  29
  30 /* DDI Descriptor: used for configuring display outputs */
  31 struct ddi_descriptor {
  32         uint8_t         connector_type; // see ddi_connector_type
  33         uint8_t         aux_index;
  34         uint8_t         hdp_index;
  35 };
  36
  37 #define USB2_PORT_COUNT 8
  38 #define USB3_PORT_COUNT 3
  39 #define USBC_COMBO_PHY_COUNT 3
  40
  41 struct fch_usb2_phy {
  42         uint8_t compdistune;            ///< COMPDISTUNE
  43         uint8_t pllbtune;               ///< PLLBTUNE
  44         uint8_t pllitune;               ///< PLLITUNE
  45         uint8_t pllptune;               ///< PLLPTUNE
  46         uint8_t sqrxtune;               ///< SQRXTUNE
  47         uint8_t txfslstune;             ///< TXFSLSTUNE
  48         uint8_t txpreempamptune;        ///< TXPREEMPAMPTUNE
  49         uint8_t txpreemppulsetune;      ///< TXPREEMPPULSETUNE
  50         uint8_t txrisetune;             ///< TXRISETUNE
  51         uint8_t txvreftune;             ///< TXVREFTUNE
  52         uint8_t txhsxvtune;             ///< TXHSXVTUNE
  53         uint8_t txrestune;              ///< TXRESTUNE
  54 };
  55
  56 struct fch_usb3_phy {
  57         uint8_t tx_term_ctrl;           ///< tx_term_ctrl
  58         uint8_t rx_term_ctrl;           ///< rx_term_ctrl
  59         uint8_t tx_vboost_lvl_en;       ///< TX_VBOOST_LVL_EN
  60         uint8_t tx_vboost_lvl;          ///< TX_VBOOST_LVL
  61 };
  62
  63 #define USB0_PORT0      0
  64 #define USB0_PORT1      1
  65 #define USB0_PORT2      1
  66 #define USB0_PORT3      3
  67 #define USB1_PORT0      (0<<2)
  68 #define USB1_PORT1      (1<<2)
  69 #define USB1_PORT2      (1<<2)
  70 #define USB1_PORT3      (3<<2)
  71
  72 #define USB_COMBO_PHY_MODE_USB_C        0
  73 #define USB_COMBO_PHY_MODE_USB_ONLY     1
  74 #define USB_COMBO_PHY_MODE_USB_DPM      2
  75 #define USB_COMBO_PHY_MODE_USB_DPP      3
  76
  77 struct usb_phy_config {
  78         struct fch_usb2_phy     Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
  79         struct fch_usb3_phy     Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
  80         uint8_t                 BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  81         uint8_t                 PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  82         uint8_t                 ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
  83 };
  84
  85 #endif /* PHOENIX_CHIP_OPENSIL_H */