src/soc/amd/picasso/acpi/soc.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/amd/common/acpi/pci_root.asl>
   4 #include "globalnvs.asl"
   5
   6 /* Power state notification to ALIB */
   7 #include "pnot.asl"
   8
   9 /* Contains the supported sleep states for this chipset */
  10 #include <soc/amd/common/acpi/sleepstates.asl>
  11
  12 /* Contains _SWS methods */
  13 #include <soc/amd/common/acpi/acpi_wake_source.asl>
  14
  15 /* System Bus */
  16 Scope(\_SB) { /* Start \_SB scope */
  17         /* global utility methods expected within the \_SB scope */
  18         #include <arch/x86/acpi/globutil.asl>
  19
  20         ROOT_BRIDGE(PCI0)
  21
  22         Scope(PCI0) {
  23                 /* Describe the AMD Northbridge */
  24                 #include "northbridge.asl"
  25
  26                 /* Describe the AMD Fusion Controller Hub */
  27                 #include <soc/amd/common/acpi/lpc.asl>
  28                 #include <soc/amd/common/acpi/platform.asl>
  29         }
  30
  31         /* PCI IRQ mapping for the Southbridge */
  32         #include "pci_int_defs.asl"
  33
  34         /* Describe PCI INT[A-H] for the Southbridge */
  35         #include <soc/amd/common/acpi/pci_int.asl>
  36
  37         /* Describe the MMIO devices in the FCH */
  38         #include "mmio.asl"
  39
  40         /* Add GPIO library */
  41         #include <soc/amd/common/acpi/gpio_bank_lib.asl>
  42
  43         #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
  44         #include <soc/amd/common/acpi/dptc.asl>
  45         #endif
  46
  47 } /* End \_SB scope */