src/soc/amd/stoneyridge/acpi/soc.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/amd/common/acpi/pci_root.asl>
   4
   5 ROOT_BRIDGE(PCI0)
   6
   7 Scope(PCI0) {
   8         /* Describe the AMD Northbridge */
   9         #include "northbridge.asl"
  10
  11         /* Describe the AMD Fusion Controller Hub */
  12         #include "sb_pci0_fch.asl"
  13 }
  14
  15 /* Describe PCI INT[A-H] for the Southbridge */
  16 #include "pci_int.asl"
  17
  18 /* Describe the MMIO devices in the FCH */
  19 #include "mmio.asl"
  20
  21 /* Add GPIO library */
  22 #include <soc/amd/common/acpi/gpio_bank_lib.asl>