mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
[coreboot2.git] / src / soc / amd / stoneyridge / fch.c
blob8729a14dea790eac188b9c4c6ed7a8a250d394f0
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <bootstate.h>
5 #include <cpu/x86/smm.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ops.h>
9 #include <acpi/acpi_gnvs.h>
10 #include <amdblocks/amd_pci_util.h>
11 #include <amdblocks/aoac.h>
12 #include <amdblocks/acpimmio.h>
13 #include <amdblocks/acpi.h>
14 #include <amdblocks/smi.h>
15 #include <soc/southbridge.h>
16 #include <soc/smi.h>
17 #include <soc/amd_pci_int_defs.h>
18 #include <soc/pci_devs.h>
19 #include <agesa_headers.h>
20 #include <soc/acpi.h>
21 #include <soc/aoac_defs.h>
22 #include <soc/nvs.h>
23 #include <static.h>
24 #include <types.h>
27 * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
28 * provides a visible association with the index, therefore helping
29 * maintainability of table. If a new index/name is defined in
30 * amd_pci_int_defs.h, just add the pair at the end of this table.
31 * Order is not important.
33 static const struct irq_idx_name irq_association[] = {
34 { PIRQ_A, "INTA#" },
35 { PIRQ_B, "INTB#" },
36 { PIRQ_C, "INTC#" },
37 { PIRQ_D, "INTD#" },
38 { PIRQ_E, "INTE#" },
39 { PIRQ_F, "INTF#" },
40 { PIRQ_G, "INTG#" },
41 { PIRQ_H, "INTH#" },
42 { PIRQ_MISC, "Misc" },
43 { PIRQ_MISC0, "Misc0" },
44 { PIRQ_MISC1, "Misc1" },
45 { PIRQ_MISC2, "Misc2" },
46 { PIRQ_SIRQA, "Ser IRQ INTA" },
47 { PIRQ_SIRQB, "Ser IRQ INTB" },
48 { PIRQ_SIRQC, "Ser IRQ INTC" },
49 { PIRQ_SIRQD, "Ser IRQ INTD" },
50 { PIRQ_SCI, "SCI" },
51 { PIRQ_SMBUS, "SMBUS" },
52 { PIRQ_ASF, "ASF" },
53 { PIRQ_HDA, "HDA" },
54 { PIRQ_FC, "FC" },
55 { PIRQ_PMON, "PerMon" },
56 { PIRQ_SD, "SD" },
57 { PIRQ_SDIO, "SDIOt" },
58 { PIRQ_EHCI, "EHCI" },
59 { PIRQ_XHCI, "XHCI" },
60 { PIRQ_SATA, "SATA" },
61 { PIRQ_GPIO, "GPIO" },
62 { PIRQ_I2C0, "I2C0" },
63 { PIRQ_I2C1, "I2C1" },
64 { PIRQ_I2C2, "I2C2" },
65 { PIRQ_I2C3, "I2C3" },
66 { PIRQ_UART0, "UART0" },
67 { PIRQ_UART1, "UART1" },
70 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
72 *size = ARRAY_SIZE(irq_association);
73 return irq_association;
76 static void fch_init_acpi_ports(void)
78 u32 reg;
80 /* We use some of these ports in SMM regardless of whether or not
81 * ACPI tables are generated. Enable these ports indiscriminately.
84 pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
85 pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
86 pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
87 pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
88 /* CpuControl is in \_SB.CP00, 6 bytes */
89 pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
91 if (CONFIG(HAVE_SMI_HANDLER)) {
92 /* APMC - SMI Command Port */
93 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
94 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
96 /* SMI on SlpTyp requires sending SMI before completion
97 * response of the I/O write. The BKDG also specifies
98 * clearing ForceStpClkRetry for SMI trapping.
100 reg = pm_read32(PM_PCI_CTRL);
101 reg |= FORCE_SLPSTATE_RETRY;
102 reg &= ~FORCE_STPCLK_RETRY;
103 pm_write32(PM_PCI_CTRL, reg);
105 /* Disable SlpTyp feature */
106 reg = pm_read8(PM_RST_CTRL1);
107 reg &= ~SLPTYPE_CONTROL_EN;
108 pm_write8(PM_RST_CTRL1, reg);
110 configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
111 } else {
112 pm_write16(PM_ACPI_SMI_CMD, 0);
115 /* Decode ACPI registers and enable standard features */
116 pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
117 PM_ACPI_GLOBAL_EN |
118 PM_ACPI_RTC_EN_EN |
119 PM_ACPI_TIMER_EN_EN);
122 void fch_init(void *chip_info)
124 fch_init_acpi_ports();
127 static void set_sb_aoac(struct aoac_devs *aoac)
129 aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0);
130 aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1);
131 aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2);
132 aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3);
133 aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0);
134 aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1);
135 aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2);
136 aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3);
138 /* Rely on these being in sync with devicetree */
139 aoac->sd_e = is_dev_enabled(DEV_PTR(sdhci)) ? 1 : 0;
140 aoac->st_e = is_dev_enabled(DEV_PTR(sata)) ? 1 : 0;
141 aoac->espi = 1;
144 static void set_sb_gnvs(struct global_nvs *gnvs)
146 uintptr_t amdfw_rom;
147 uintptr_t xhci_fw;
148 uintptr_t fwaddr;
149 size_t fwsize;
151 amdfw_rom = 4ull * GiB - CONFIG_ROM_SIZE + CONFIG_AMD_FWM_POSITION;
152 xhci_fw = read32p(amdfw_rom + XHCI_FW_SIG_OFFSET);
154 fwaddr = 2 + read16p(xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE);
155 fwsize = read16p(xhci_fw + XHCI_FW_SIZE_OFFSET + XHCI_FW_BOOTRAM_SIZE);
156 gnvs->fw00 = 0;
157 gnvs->fw01 = ((32 * KiB) << 16) + 0;
158 gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
159 gnvs->fw03 = fwsize << 16;
161 /* TODO: This might break if the OS decides to re-allocate the PCI BARs. */
162 gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
163 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
166 void fch_final(void *chip_info)
168 /* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */
169 struct global_nvs *gnvs = acpi_get_gnvs();
170 if (gnvs) {
171 set_sb_aoac(&gnvs->aoac);
172 set_sb_gnvs(gnvs);
177 * Update the PCI devices with a valid IRQ number
178 * that is set in the mainboard PCI_IRQ structures.
180 static void set_pci_irqs(void *unused)
182 /* Write PCI_INTR regs 0xC00/0xC01 */
183 write_pci_int_table();
185 /* Write IRQs for all devicetree enabled devices */
186 write_pci_cfg_irqs();
190 * Hook this function into the PCI state machine
191 * on entry into BS_DEV_ENABLE.
193 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);