1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
7 #define __SIMPLE_DEVICE__
9 #include <device/pci_ops.h>
10 #include <device/pci.h>
11 #include <soc/addressmap.h>
15 * Get PCI BAR address from cavium specific extended capability.
16 * Use regular BAR if not found in extended capability space.
18 * @return The physical address of the BAR, zero on error
20 uint64_t ecam0_get_bar_val(pci_devfn_t dev
, u8 bar
)
22 size_t cap_offset
= pci_s_find_capability(dev
, 0x14);
23 uint64_t h
, l
, ret
= 0;
27 u8 ne
= pci_read_config8(dev
, cap_offset
+ 2) & 0x3f;
31 uint32_t dw0
= pci_read_config32(dev
, cap_offset
);
34 bei
= (dw0
>> 4) & 0xf;
37 l
= pci_read_config32(dev
, cap_offset
+ 4);
39 h
= pci_read_config32(dev
,
41 ret
= (h
<< 32) | (l
& ~0xfull
);
44 cap_offset
+= (es
+ 1) * 4;
49 l
= pci_read_config32(dev
, bar
* 4 + PCI_BASE_ADDRESS_0
);
51 h
= pci_read_config32(dev
, bar
* 4 + PCI_BASE_ADDRESS_0
53 ret
= (h
<< 32) | (l
& ~0xfull
);