soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / soc / cavium / common / pci / chip.h
blobbe5f3fa801f1ac8628f0e5debddefcc9435217a5
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H
4 #define __SOC_CAVIUM_COMMON_PCI_CHIP_H
6 struct soc_cavium_common_pci_config {
7 /**
8 * Mark the PCI device as secure.
9 * It will be visible from EL3, but hidden in EL2-0.
11 u8 secure;
14 #endif /* __SOC_CAVIUM_COMMON_PCI_CHIP_H */