src/soc/intel/alderlake/soundwire.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi_soundwire.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/soundwire.h>
   7 #include <drivers/intel/soundwire/soundwire.h>
   8 #include <intelblocks/pmclib.h>
   9 #include <stddef.h>
  10 #include <string.h>
  11
  12 static const struct soundwire_link link_xtal_38_4 = {
  13         .clock_stop_mode0_supported = 1,
  14         .clock_stop_mode1_supported = 1,
  15         .clock_frequencies_supported_count = 1,
  16         .clock_frequencies_supported = { 4800 * KHz },
  17         .default_frame_rate = 48 * KHz,
  18         .default_frame_row_size = 50,
  19         .default_frame_col_size = 4,
  20         .dynamic_frame_shape = 1,
  21         .command_error_threshold = 16,
  22 };
  23
  24 static const struct soundwire_link link_xtal_24 = {
  25         .clock_stop_mode0_supported = 1,
  26         .clock_stop_mode1_supported = 1,
  27         .clock_frequencies_supported_count = 1,
  28         .clock_frequencies_supported = { 6 * MHz },
  29         .default_frame_rate = 48 * KHz,
  30         .default_frame_row_size = 125,
  31         .default_frame_col_size = 2,
  32         .dynamic_frame_shape = 1,
  33         .command_error_threshold = 16,
  34 };
  35
  36 static struct intel_soundwire_controller intel_controller = {
  37         .acpi_address = 0x40000000,
  38         .sdw = {
  39                 .master_list_count = 4
  40         }
  41 };
  42
  43 int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
  44 {
  45         const struct soundwire_link *link;
  46         enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
  47         size_t i;
  48
  49         /* Select link config based on XTAL frequency and set IP clock. */
  50         switch (xtal) {
  51         case XTAL_24_MHZ:
  52                 link = &link_xtal_24;
  53                 intel_controller.ip_clock = 24 * MHz;
  54                 break;
  55         case XTAL_38_4_MHZ:
  56                 link = &link_xtal_38_4;
  57                 intel_controller.ip_clock = 38400 * KHz;
  58                 break;
  59         case XTAL_19_2_MHZ:
  60         default:
  61                 printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
  62                 return -1;
  63         }
  64
  65         /* Fill link config in controller map based on selected XTAL. */
  66         for (i = 0; i < intel_controller.sdw.master_list_count; i++)
  67                 memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
  68
  69         *controller = &intel_controller;
  70         return 0;
  71 }