src/soc/intel/apollolake/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2 ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
   3
   4 subdirs-y += ../../../cpu/intel/common
   5 subdirs-y += ../../../cpu/intel/microcode
   6 subdirs-y += ../../../cpu/intel/turbo
   7
   8 bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock/bootblock_measure.c
   9 bootblock-y += bootblock/bootblock.c
  10 bootblock-y += ../common/block/cpu/pm_timer_emulation.c
  11 bootblock-y += car.c
  12 bootblock-y += heci.c
  13 bootblock-y += gspi.c
  14 bootblock-y += i2c.c
  15 bootblock-y += lpc.c
  16 bootblock-y += mmap_boot.c
  17 bootblock-y += pmutil.c
  18 bootblock-y += spi.c
  19 bootblock-y += uart.c
  20
  21 romstage-y += car.c
  22 romstage-y += ../../../cpu/intel/car/romstage.c
  23 romstage-y += romstage.c
  24 romstage-y += report_platform.c
  25 romstage-y += gspi.c
  26 romstage-y += heci.c
  27 romstage-y += i2c.c
  28 romstage-y += uart.c
  29 romstage-y += meminit.c
  30 ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
  31 romstage-y += meminit_util_glk.c
  32 else
  33 romstage-y += meminit_util_apl.c
  34 endif
  35 romstage-y += mmap_boot.c
  36 romstage-y += pmutil.c
  37 romstage-y += reset.c
  38 romstage-y += spi.c
  39
  40 smm-y += mmap_boot.c
  41 smm-y += pmutil.c
  42 smm-y += smihandler.c
  43 smm-y += spi.c
  44 smm-y += uart.c
  45 smm-y += elog.c
  46 smm-y += xhci.c
  47
  48 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
  49 ramstage-y += ahci.c
  50 ramstage-y += cpu.c
  51 ramstage-y += chip.c
  52 ramstage-y += cse.c
  53 ramstage-y += elog.c
  54 ramstage-y += graphics.c
  55 ramstage-y += gspi.c
  56 ramstage-y += heci.c
  57 ramstage-y += i2c.c
  58 ramstage-y += lockdown.c
  59 ramstage-y += lpc.c
  60 ramstage-y += mmap_boot.c
  61 ramstage-y += uart.c
  62 ramstage-y += nhlt.c
  63 ramstage-y += spi.c
  64 ramstage-y += systemagent.c
  65 ramstage-y += pmutil.c
  66 ramstage-y += pnpconfig.c
  67 ramstage-y += pmc.c
  68 ramstage-y += reset.c
  69 ramstage-y += xdci.c
  70 ramstage-y += sd.c
  71 ramstage-y += xhci.c
  72
  73 postcar-y += mmap_boot.c
  74 postcar-y += spi.c
  75 postcar-y += i2c.c
  76 postcar-y += heci.c
  77 postcar-y += reset.c
  78 postcar-y += uart.c
  79 postcar-y += gspi.c
  80
  81 verstage-y += car.c
  82 verstage-y += i2c.c
  83 verstage-y += gspi.c
  84 verstage-y += heci.c
  85 verstage-y += mmap_boot.c
  86 verstage-y += uart.c
  87 verstage-y += pmutil.c
  88 verstage-y += reset.c
  89 verstage-y += spi.c
  90
  91 ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
  92 bootblock-y += gpio_glk.c
  93 romstage-y += gpio_glk.c
  94 smm-y += gpio_glk.c
  95 ramstage-y += gpio_glk.c
  96 verstage-y += gpio_glk.c
  97 else
  98 bootblock-y += gpio_apl.c
  99 romstage-y += gpio_apl.c
 100 smm-y += gpio_apl.c
 101 ramstage-y += gpio_apl.c
 102 verstage-y += gpio_apl.c
 103 endif
 104
 105 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 106
 107 # Since FSP-M runs in CAR we need to relocate it to a specific address
 108 $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
 109
 110 # Handle GLK paging requirements
 111 ifeq ($(CONFIG_PAGING_IN_CACHE_AS_RAM),y)
 112 cbfs-files-y += pt
 113 pt-file := pt.c:struct
 114 pt-type := raw
 115 cbfs-files-y += pdpt
 116 pdpt-file := pdpt.c:struct
 117 pdpt-type := raw
 118 endif
 119
 120 ifeq ($(CONFIG_NEED_LBP2),y)
 121 $(objcbfs)/lbp2.bin: $(IFWITOOL)
 122 ifeq ($(CONFIG_LBP2_FROM_IFWI),y)
 123         $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $@ -s
 124         $(IFWITOOL) $@ delete -n OBBP
 125 else
 126         cp $(CONFIG_LBP2_FILE_NAME) $@
 127 endif
 128
 129 $(call add_intermediate, write_lbp2, $(objcbfs)/lbp2.bin)
 130         @printf "    FMAP      writing lbp2 to %s\n" $(CONFIG_LBP2_FMAP_NAME)
 131         $(CBFSTOOL) $< write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward
 132 endif
 133
 134 # Bootblock on Apollolake platform lies in the IFWI region. In order to place
 135 # the bootblock at the right location in IFWI image -
 136 # a. Using ifwitool:
 137 #    1. Create IFWI image (ifwi.bin.tmp) from input image
 138 #       (CONFIG_IFWI_FILE_NAME).
 139 #    2. Delete OBBP sub-partition, if present.
 140 #    3. Replace IBBL directory entry in IBBP sub-partition with currently
 141 #       generated bootblock.bin.
 142 # b. Using cbfstool:
 143 #    1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
 144 ifeq ($(CONFIG_NEED_IFWI),y)
 145 $(call add_intermediate, write_ifwi, $(objcbfs)/bootblock.bin $(IFWITOOL))
 146         @printf "    IFWI       Embedding %s in %s\n" $(objcbfs)/bootblock.bin $(CONFIG_IFWI_FMAP_NAME)
 147         $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
 148         $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
 149         $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
 150         $(CBFSTOOL) $< write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
 151 endif
 152
 153 # When booting APL the IBBL loader places the microcode updates embedded
 154 # in the IFWI image and a matching FIT table in SRAM. After copying the
 155 # bootblock to SRAM, it updates the FIT pointer at 0xffffffc0 to point
 156 # to that table. Before releasing the x86 cores from reset, the regular FIT
 157 # mechanism does the updates. So coreboot does not need to generate a FIT
 158 # table + pointer, but reserving the pointer is still needed. Otherwise the
 159 # IBBL loader thrashes code there. So include fit.c so that the linker
 160 # reserves that pointer.
 161 bootblock-y += bootblock/fit.c
 162
 163 # DSP firmware settings files.
 164 ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
 165 NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs
 166 else
 167 NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs
 168 endif
 169 DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
 170 DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
 171 DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
 172 MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
 173 DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
 174 RT5682_RENDER_CAPTURE = rt5682-2ch-48khz-24b.bin
 175
 176 cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)
 177 $(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
 178 $(DMIC_1CH_48KHZ_16B)-type := raw
 179
 180 cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)
 181 $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
 182 $(DMIC_2CH_48KHZ_16B)-type := raw
 183
 184 cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)
 185 $(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
 186 $(DMIC_4CH_48KHZ_16B)-type := raw
 187
 188 cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
 189 $(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
 190 $(MAX98357_RENDER)-type := raw
 191
 192 cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
 193 $(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
 194 $(DA7219_RENDER_CAPTURE)-type := raw
 195
 196 cbfs-files-$(CONFIG_NHLT_RT5682) += $(RT5682_RENDER_CAPTURE)
 197 $(RT5682_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(RT5682_RENDER_CAPTURE)
 198 $(RT5682_RENDER_CAPTURE)-type := raw
 199
 200 ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y)
 201 # Gemini Lake B0 (706a1) only atm.
 202 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*)
 203 else
 204 # Apollo Lake 506c2, B0 (506c9) and E0 (506ca) only atm.
 205 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*)
 206 endif
 207
 208 endif # if CONFIG_SOC_INTEL_APOLLOLAKE