src/soc/intel/apollolake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <console/console.h>
   8 #include <device/device.h>
   9 #include <device/mmio.h>
  10 #include <arch/smp/mpspec.h>
  11 #include <assert.h>
  12 #include <device/pci_ops.h>
  13 #include <gpio.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/pmclib.h>
  16 #include <intelblocks/p2sb.h>
  17 #include <soc/iomap.h>
  18 #include <soc/pm.h>
  19 #include <soc/nvs.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/systemagent.h>
  22 #include <static.h>
  23
  24 #include "chip.h"
  25
  26 #define CSTATE_RES(address_space, width, offset, address)               \
  27         {                                                               \
  28         .space_id = address_space,                                      \
  29         .bit_width = width,                                             \
  30         .bit_offset = offset,                                           \
  31         .addrl = address,                                               \
  32         }
  33
  34 static const acpi_cstate_t cstate_map[] = {
  35         {
  36                 /* C1 */
  37                 .ctype = 1,             /* ACPI C1 */
  38                 .latency = 1,
  39                 .power = 1000,
  40                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0),
  41         },
  42         {
  43                 .ctype = 2,             /* ACPI C2 */
  44                 .latency = 50,
  45                 .power = 10,
  46                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415),
  47         },
  48         {
  49                 .ctype = 3,             /* ACPI C3 */
  50                 .latency = 150,
  51                 .power = 10,
  52                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419),
  53         }
  54 };
  55
  56 uint32_t soc_read_sci_irq_select(void)
  57 {
  58         return read32p(soc_read_pmc_base() + IRQ_REG);
  59 }
  60
  61 void soc_write_sci_irq_select(uint32_t scis)
  62 {
  63         write32p(soc_read_pmc_base() + IRQ_REG, scis);
  64 }
  65
  66 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  67 {
  68         *entries = ARRAY_SIZE(cstate_map);
  69         return cstate_map;
  70 }
  71
  72 void soc_fill_gnvs(struct global_nvs *gnvs)
  73 {
  74         struct soc_intel_apollolake_config *cfg;
  75         cfg = config_of_soc();
  76
  77         /* Enable DPTF based on mainboard configuration */
  78         gnvs->dpte = cfg->dptf_enable;
  79
  80         /* Assign address of PERST_0 if GPIO is defined in devicetree */
  81         if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
  82                 gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
  83
  84         /* Get sdcard cd GPIO portid if GPIO is defined in devicetree.
  85          * Get offset of sdcard cd pin.
  86          */
  87         if (cfg->sdcard_cd_gpio) {
  88                 gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio);
  89                 gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
  90         }
  91 }
  92
  93 int soc_madt_sci_irq_polarity(int sci)
  94 {
  95         return MP_IRQ_POLARITY_LOW;
  96 }
  97
  98 void soc_fill_fadt(acpi_fadt_t *fadt)
  99 {
 100         const struct soc_intel_apollolake_config *cfg;
 101         cfg = config_of_soc();
 102
 103         fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
 104
 105         fadt->pm_tmr_len = 4;
 106
 107         fill_fadt_extended_pm_io(fadt);
 108
 109         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 110
 111         if (cfg->lpss_s0ix_enable)
 112                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 113 }
 114
 115 static unsigned long soc_fill_dmar(unsigned long current)
 116 {
 117         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 118         uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
 119         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 120         bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED;
 121         unsigned long tmp;
 122
 123         /* IGD has to be enabled, GFXVTBAR set and enabled. */
 124         const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
 125
 126         /* First, add DRHD entries */
 127         if (emit_igd) {
 128                 tmp = current;
 129
 130                 current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
 131                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 132                 acpi_dmar_drhd_fixup(tmp, current);
 133         }
 134
 135         /* DEFVTBAR has to be set and enabled. */
 136         if (defvtbar && defvten) {
 137                 tmp = current;
 138                 union p2sb_bdf ibdf = p2sb_get_ioapic_bdf();
 139                 union p2sb_bdf hbdf = p2sb_get_hpet_bdf();
 140                 p2sb_hide();
 141
 142                 current += acpi_create_dmar_drhd_4k(current,
 143                                 DRHD_INCLUDE_PCI_ALL, 0, defvtbar);
 144                 current += acpi_create_dmar_ds_ioapic_from_hw(current,
 145                                 IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn);
 146                 current += acpi_create_dmar_ds_msi_hpet(current,
 147                                 0, hbdf.bus, hbdf.dev, hbdf.fn);
 148                 acpi_dmar_drhd_fixup(tmp, current);
 149         }
 150
 151         /* Then, add RMRR entries after all DRHD entries */
 152         if (emit_igd) {
 153                 tmp = current;
 154                 current += acpi_create_dmar_rmrr(current, 0,
 155                                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 156                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 157                 acpi_dmar_rmrr_fixup(tmp, current);
 158         }
 159
 160         return current;
 161 }
 162
 163 unsigned long sa_write_acpi_tables(const struct device *const dev,
 164                                      unsigned long current,
 165                                      struct acpi_rsdp *const rsdp)
 166 {
 167         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 168
 169         /* Create DMAR table only if virtualization is enabled. Due to some
 170          * constraints on Apollo Lake SoC (some stepping affected), VTD could
 171          * not be enabled together with IPU. Doing so will override and disable
 172          * VTD while leaving CAPID0_A still reporting that VTD is available.
 173          * As in this case FSP will lock VTD to disabled state, we need to make
 174          * sure that DMAR table generation only happens when at least DEFVTBAR
 175          * is enabled. Otherwise the DMAR header will be generated while the
 176          * content of the table will be missing.
 177          */
 178
 179         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 180             !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
 181                 return current;
 182
 183         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 184         acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
 185         current += dmar->header.length;
 186         current = acpi_align_current(current);
 187         acpi_add_table(rsdp, dmar);
 188         current = acpi_align_current(current);
 189
 190         return current;
 191 }
 192
 193 void soc_power_states_generation(int core_id, int cores_per_package)
 194 {
 195         /* Generate P-state tables */
 196         generate_p_state_entries(core_id, cores_per_package);
 197
 198         /* Generate T-state tables */
 199         generate_t_state_entries(core_id, cores_per_package);
 200 }
 201
 202 static void acpigen_soc_get_dw0_in_local5(uintptr_t addr)
 203 {
 204         /*
 205          * Store (\_SB.GPC0 (addr), Local5)
 206          * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in
 207          * gpiolib.asl.
 208          */
 209         acpigen_write_store();
 210         acpigen_emit_namestring("\\_SB.GPC0");
 211         acpigen_write_integer(addr);
 212         acpigen_emit_byte(LOCAL5_OP);
 213 }
 214
 215 static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 216 {
 217         assert(gpio_num < TOTAL_PADS);
 218         uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
 219
 220         acpigen_soc_get_dw0_in_local5(addr);
 221
 222         /* If (And (Local5, mask)) */
 223         acpigen_write_if_and(LOCAL5_OP, mask);
 224
 225         /* Store (One, Local0) */
 226         acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
 227
 228         /* Else */
 229         acpigen_write_else();
 230
 231         /* Store (Zero, Local0) */
 232         acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
 233
 234         acpigen_pop_len();      /* Else */
 235
 236         return 0;
 237 }
 238
 239 static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 240 {
 241         assert(gpio_num < TOTAL_PADS);
 242         uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
 243
 244         acpigen_soc_get_dw0_in_local5(addr);
 245
 246         if (val) {
 247                 /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */
 248                 acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP);
 249         } else {
 250                 /* Not (PAD_CFG0_TX_STATE, Local6) */
 251                 acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP);
 252
 253                 /* And (Local5, Local6, Local5) */
 254                 acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
 255         }
 256
 257         /*
 258          * \_SB.SPC0 (addr, Local5)
 259          * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in
 260          * gpiolib.asl.
 261          */
 262         acpigen_emit_namestring("\\_SB.SPC0");
 263         acpigen_write_integer(addr);
 264         acpigen_emit_byte(LOCAL5_OP);
 265
 266         return 0;
 267 }
 268
 269 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 270 {
 271         return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE);
 272 }
 273
 274 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 275 {
 276         return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE);
 277 }
 278
 279 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 280 {
 281         return acpigen_soc_set_gpio_val(gpio_num, 1);
 282 }
 283
 284 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 285 {
 286         return acpigen_soc_set_gpio_val(gpio_num, 0);
 287 }