src/soc/intel/apollolake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef _SOC_APOLLOLAKE_CHIP_H_
   4 #define _SOC_APOLLOLAKE_CHIP_H_
   5
   6 #include <commonlib/helpers.h>
   7 #include <drivers/intel/gma/gma.h>
   8 #include <intelblocks/cfg.h>
   9 #include <intelblocks/gspi.h>
  10 #include <gpio.h>
  11 #include <soc/gpe.h>
  12 #include <intelblocks/lpc_lib.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <device/i2c_simple.h>
  15 #include <drivers/i2c/designware/dw_i2c.h>
  16 #include <soc/pm.h>
  17 #include <soc/usb.h>
  18
  19 #define MAX_PCIE_PORTS                  6
  20 #define CLKREQ_DISABLED         0xf
  21
  22 enum pnp_settings {
  23         PNP_PERF,
  24         PNP_POWER,
  25         PNP_PERF_POWER,
  26 };
  27
  28 enum sata_speed_limit {
  29         SATA_DEFAULT = 0,
  30         SATA_GEN1,
  31         SATA_GEN2,
  32         SATA_GEN3
  33 };
  34
  35 struct soc_intel_apollolake_config {
  36         /* Common structure containing soc config data required by common code*/
  37         struct soc_intel_common_config common_soc_config;
  38
  39         /* Common struct containing power limits configuration info */
  40         struct soc_power_limits_config power_limits_config;
  41
  42         /*
  43          * IGD panel configuration
  44          *
  45          * Second backlight control shares logic with other pins (aka. display utility pin).
  46          * Be sure it's used for PWM before setting any secondary backlight value.
  47          */
  48         struct i915_gpu_panel_config panel_cfg[2];
  49
  50         /* i915 struct for GMA backlight control */
  51         struct i915_gpu_controller_info gfx;
  52
  53         /*
  54          * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
  55          * four CLKREQ inputs, but six root ports. Root ports without an
  56          * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
  57          */
  58         uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
  59
  60         /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */
  61         bool pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
  62
  63         /* De-emphasis enable configuration for each PCIe root port */
  64         bool pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
  65
  66         /* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
  67          * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
  68          */
  69         uint32_t emmc_tx_cmd_cntl;
  70
  71         /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
  72          * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
  73          */
  74         uint32_t emmc_tx_data_cntl1;
  75
  76         /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  77          * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  78          * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  79          * [6:0] SDR12/Compatibility mode Number of dealy elements.
  80          *       Each = 125pSec.
  81          */
  82         uint32_t emmc_tx_data_cntl2;
  83
  84         /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  85          * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  86          * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  87          * [6:0] SDR12/Compatibility mode Number of dealy elements.
  88          *       Each = 125pSec.
  89          */
  90         uint32_t emmc_rx_cmd_data_cntl1;
  91
  92         /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
  93          * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
  94          */
  95         uint32_t emmc_rx_strobe_cntl;
  96
  97         /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
  98          * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
  99          */
 100         uint32_t emmc_rx_cmd_data_cntl2;
 101
 102         /* Select the eMMC max speed allowed. */
 103         uint8_t emmc_host_max_speed;
 104
 105         /* Sata Ports Hot Plug */
 106         bool sata_ports_hot_plug[2];
 107
 108         /* Sata Ports Enable */
 109         bool sata_ports_enable[2];
 110
 111         /* Sata Ports Solid State Drive */
 112         uint8_t sata_ports_ssd[2];
 113
 114         /* Specifies on which IRQ the SCI will internally appear. */
 115         uint8_t sci_irq;
 116
 117         /* Configure serial IRQ (SERIRQ) line. */
 118         enum serirq_mode serirq_mode;
 119
 120         uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
 121         uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
 122         uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
 123
 124         /* LPC fixed enables and ranges */
 125         uint16_t lpc_iod;
 126         uint16_t lpc_ioe;
 127
 128         /* Generic IO decode ranges */
 129         uint32_t gen1_dec;
 130         uint32_t gen2_dec;
 131         uint32_t gen3_dec;
 132         uint32_t gen4_dec;
 133
 134         /* Configure LPSS S0ix Enable */
 135         bool lpss_s0ix_enable;
 136
 137         /* Enable DPTF support */
 138         bool dptf_enable;
 139
 140         /* TCC activation offset value in degrees Celsius */
 141         uint32_t tcc_offset;
 142
 143         /* Configure Audio clk gate and power gate
 144          * IOSF-SB port ID 92 offset 0x530 [5] and [3]
 145          */
 146         bool hdaudio_clk_gate_enable;
 147         bool hdaudio_pwr_gate_enable;
 148         bool hdaudio_bios_config_lockdown;
 149
 150         /* Enhanced C-states */
 151         bool enhanced_cstates;
 152
 153         /* SLP S3 minimum assertion width. */
 154         int slp_s3_assertion_width_usecs;
 155
 156         /* GPIO pin for PERST_0 */
 157         uint16_t prt0_gpio;
 158
 159         /* USB2 eye diagram settings per port */
 160         struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
 161
 162         /* Override USB port configuration */
 163         bool usb_config_override;
 164         struct usb_port_config usb2_port[APOLLOLAKE_USB2_PORT_MAX];
 165         struct usb_port_config usb3_port[APOLLOLAKE_USB3_PORT_MAX];
 166
 167         /* GPIO SD card detect pin */
 168         unsigned int sdcard_cd_gpio;
 169
 170         /* Select PNP Settings.
 171          * (0) Performance,
 172          * (1) Power
 173          * (2) Power & Performance */
 174         enum pnp_settings pnp_settings;
 175
 176         /* PMIC PCH_PWROK delay configuration - IPC Configuration
 177          * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
 178          * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
 179          */
 180         uint32_t pmic_pmc_ipc_ctrl;
 181
 182         /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
 183          * disable Compliance Mode. Set TRUE to disable Compliance Mode.
 184          * 0:FALSE(Default), 1:True.
 185          */
 186         bool disable_compliance_mode;
 187
 188         /* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
 189          * value. Default is 0 to not changing default IF value (0x12). Set
 190          * value with the range from 0x01 to 0xff to change IF value.
 191          */
 192         uint8_t mod_phy_if_value;
 193
 194         /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
 195          * LDO voltage. Set TRUE to increase LDO voltage with 40mV.
 196          * 0:FALSE (default), 1:True.
 197          */
 198         bool mod_phy_voltage_bump;
 199
 200         /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
 201          * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
 202          * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
 203          * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
 204          * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
 205          */
 206         uint32_t pmic_vdd2_voltage;
 207
 208         /* Option to enable VTD feature. Default is 0 which disables VTD
 209          * capability in FSP. Setting this option to 1 in devicetree will enable
 210          * the Upd parameter VtdEnable.
 211          */
 212         bool enable_vtd;
 213
 214         /* Options to disable the LFPS periodic sampling for USB3 Ports.
 215          * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic sampling
 216          * interval is 9ms.
 217          * Set 1 to update XHCI host MMIO BAR + PMCTRL_REG (0x80A4 bits[7:4]) to 0
 218          * 0:Enable (default), 1:Disable.
 219          */
 220         bool disable_xhci_lfps_pm;
 221
 222         /* SATA Aggressive Link Power Management */
 223         bool disable_sata_salp_support;
 224
 225         /* Sata Power Optimisation */
 226         bool sata_pwr_optimize_disable;
 227
 228         /* SATA speed limit */
 229         enum sata_speed_limit sata_speed;
 230 };
 231
 232 typedef struct soc_intel_apollolake_config config_t;
 233
 234 #endif  /* _SOC_APOLLOLAKE_CHIP_H_ */