src/soc/intel/apollolake/graphics.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <stdint.h>
   4 #include <commonlib/helpers.h>
   5 #include <device/device.h>
   6 #include <device/mmio.h>
   7 #include <device/pci_def.h>
   8 #include <intelblocks/graphics.h>
   9 #include <drivers/intel/gma/i915_reg.h>
  10
  11 #include "chip.h"
  12
  13 static void graphics_configure_panelpower(
  14                 const struct i915_gpu_panel_config *const panel_cfg,
  15                 uint8_t *const mmio, const unsigned int panel_idx)
  16 {
  17         const unsigned int offset = panel_idx * 0x100;
  18         uint32_t reg32;
  19
  20         reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
  21         reg32 |= PANEL_POWER_RESET;
  22         write32(mmio + PCH_PP_CONTROL + offset, reg32);
  23
  24         reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
  25         reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
  26         write32(mmio + PCH_PP_ON_DELAYS + offset, reg32);
  27
  28         reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
  29         reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
  30         write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32);
  31 }
  32
  33 static void graphics_configure_backlight(
  34                 const struct i915_gpu_panel_config *const panel_cfg,
  35                 uint8_t *const mmio, const unsigned int panel_idx)
  36 {
  37         if (!panel_cfg->backlight_pwm_hz)
  38                 return;
  39
  40         const unsigned int pwm_period = 19200 * 1000 / panel_cfg->backlight_pwm_hz;
  41         write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period);
  42         write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2);
  43         write32(mmio + BXT_BLC_PWM_CTL(panel_idx),
  44                 panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0);
  45
  46         /* Second backlight control uses display utility pin. */
  47         if (panel_idx == 1) {
  48                 write32(mmio + UTIL_PIN_CTL, 0); /* Make sure it's disabled, don't know
  49                                                     what FSP might have done already. */
  50                 write32(mmio + UTIL_PIN_CTL, UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
  51         }
  52 }
  53
  54 void graphics_soc_panel_init(struct device *const dev)
  55 {
  56         const struct soc_intel_apollolake_config *const conf = dev->chip_info;
  57         const struct resource *mmio_res;
  58         void *mmio;
  59         unsigned int i;
  60
  61         /* Some hardware configuration first. */
  62
  63         if (!conf)
  64                 return;
  65
  66         mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  67         if (!mmio_res || !mmio_res->base)
  68                 return;
  69         mmio = (void *)(uintptr_t)mmio_res->base;
  70
  71         for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
  72                 graphics_configure_panelpower(&conf->panel_cfg[i], mmio, i);
  73
  74         for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
  75                 graphics_configure_backlight(&conf->panel_cfg[i], mmio, i);
  76 }
  77
  78 const struct i915_gpu_controller_info *
  79 intel_igd_get_controller_info(const struct device *device)
  80 {
  81         struct soc_intel_apollolake_config *chip = device->chip_info;
  82         return &chip->gfx;
  83 }