src/soc/intel/apollolake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include "chip.h"
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <intelblocks/pmc.h>
   9 #include <intelblocks/pmclib.h>
  10 #include <soc/iomap.h>
  11 #include <soc/pm.h>
  12 #include <timer.h>
  13
  14 /* Fill up PMC resource structure */
  15 int pmc_soc_get_resources(struct pmc_resource_config *cfg)
  16 {
  17         cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
  18         cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
  19         cfg->pwrmbase_size = PMC_BAR0_SIZE;
  20         cfg->abase_offset = PCI_BASE_ADDRESS_4;
  21         cfg->abase_addr = ACPI_BASE_ADDRESS;
  22         cfg->abase_size = ACPI_BASE_SIZE;
  23
  24         return 0;
  25 }
  26
  27 static int choose_slp_s3_assertion_width(int width_usecs)
  28 {
  29         int i;
  30         static const struct {
  31                 int max_width;
  32                 int value;
  33         } slp_s3_settings[] = {
  34                 {
  35                         .max_width = 60,
  36                         .value = SLP_S3_ASSERT_60_USEC,
  37                 },
  38                 {
  39                         .max_width = 1 * USECS_PER_MSEC,
  40                         .value = SLP_S3_ASSERT_1_MSEC,
  41                 },
  42                 {
  43                         .max_width = 50 * USECS_PER_MSEC,
  44                         .value = SLP_S3_ASSERT_50_MSEC,
  45                 },
  46                 {
  47                         .max_width =  2 * USECS_PER_SEC,
  48                         .value = SLP_S3_ASSERT_2_SEC,
  49                 },
  50         };
  51
  52         for (i = 0; i < ARRAY_SIZE(slp_s3_settings); i++) {
  53                 if (width_usecs <= slp_s3_settings[i].max_width)
  54                         break;
  55         }
  56
  57         /* Provide conservative default if nothing set in devicetree
  58          * or requested assertion width too large. */
  59         if (width_usecs <= 0 || i == ARRAY_SIZE(slp_s3_settings))
  60                 i = ARRAY_SIZE(slp_s3_settings) - 1;
  61
  62         printk(BIOS_DEBUG, "SLP S3 assertion width: %d usecs\n",
  63                 slp_s3_settings[i].max_width);
  64
  65         return slp_s3_settings[i].value;
  66 }
  67
  68 static void set_slp_s3_assertion_width(int width_usecs)
  69 {
  70         uint32_t reg;
  71         uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
  72         int setting = choose_slp_s3_assertion_width(width_usecs);
  73
  74         reg = read32p(gen_pmcon3);
  75         reg &= ~SLP_S3_ASSERT_MASK;
  76         reg |= setting << SLP_S3_ASSERT_WIDTH_SHIFT;
  77         write32p(gen_pmcon3, reg);
  78 }
  79
  80 void pmc_soc_init(struct device *dev)
  81 {
  82         const struct soc_intel_apollolake_config *cfg = config_of(dev);
  83
  84         /* Set up GPE configuration */
  85         pmc_gpe_init();
  86         pmc_set_acpi_mode();
  87
  88         if (cfg != NULL)
  89                 set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
  90
  91         /* Log power state */
  92         pch_log_state();
  93
  94         /* Now that things have been logged clear out the PMC state. */
  95         pmc_clear_prsts();
  96
  97         pmc_set_power_failure_state(true);
  98 }