src/soc/intel/braswell/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_BRASWELL
   4         bool
   5         select ACPI_COMMON_MADT_IOAPIC
   6         select ACPI_COMMON_MADT_LAPIC
   7         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   8         select ARCH_X86
   9         select BOOT_DEVICE_SUPPORTS_WRITES
  10         select CACHE_MRC_SETTINGS
  11         select SUPPORT_CPU_UCODE_IN_CBFS
  12         select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
  13         select HAVE_SMI_HANDLER
  14         select PCIEXP_ASPM
  15         select PCIEXP_CLK_PM
  16         select PCIEXP_COMMON_CLOCK
  17         select PLATFORM_USES_FSP1_1
  18         select REG_SCRIPT
  19         select RTC
  20         select SOC_INTEL_COMMON
  21         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  22         select SOC_INTEL_COMMON_BLOCK
  23         select SOC_INTEL_COMMON_BLOCK_HDA
  24         select SOC_INTEL_COMMON_RESET
  25         select SPI_FLASH
  26         select SSE2
  27         select TSC_MONOTONIC_TIMER
  28         select TSC_SYNC_MFENCE
  29         select UDELAY_TSC
  30         select USE_GENERIC_FSP_CAR_INC
  31         select INTEL_DESCRIPTOR_MODE_CAPABLE
  32         select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
  33         select HAVE_FSP_GOP
  34         select GENERIC_GPIO_LIB
  35         select INTEL_GMA_ACPI
  36         select INTEL_GMA_SWSMISCI
  37         select CPU_INTEL_COMMON
  38         select SOUTHBRIDGE_INTEL_COMMON_SMBUS
  39         select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
  40         select NO_CBFS_MCACHE
  41         select TCO_SPACE_NOT_YET_SPLIT
  42         select NEED_SMALL_2MB_PAGE_TABLES
  43         help
  44           Braswell M/D part support.
  45
  46 if SOC_INTEL_BRASWELL
  47
  48 config DCACHE_BSP_STACK_SIZE
  49         hex
  50         default 0x2000
  51         help
  52           The amount of anticipated stack usage in CAR by bootblock and
  53           other stages.
  54
  55 config VBOOT
  56         select VBOOT_MUST_REQUEST_DISPLAY
  57         select VBOOT_STARTS_IN_ROMSTAGE
  58
  59 config ECAM_MMCONF_BASE_ADDRESS
  60         default 0xe0000000
  61
  62 config ECAM_MMCONF_BUS_NUMBER
  63         int
  64         default 256
  65
  66 config MAX_CPUS
  67         int
  68         default 4
  69
  70 config SMM_TSEG_SIZE
  71         hex
  72         default 0x800000
  73
  74 config SMM_RESERVED_SIZE
  75         hex
  76         default 0x100000
  77
  78 # Cache As RAM region layout:
  79 #
  80 # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
  81 # |  Stack      |
  82 # |    |        |
  83 # |    v        |
  84 # +-------------+
  85 # |    ^        |
  86 # |    |        |
  87 # | CAR Globals |
  88 # +-------------+ DCACHE_RAM_BASE
  89 #
  90
  91 config DCACHE_RAM_BASE
  92         hex
  93         default 0xfef00000
  94
  95 config DCACHE_RAM_SIZE
  96         hex
  97         default 0x8000
  98         help
  99           The size of the cache-as-ram region required during bootblock
 100           and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 101           must add up to a power of 2.
 102
 103 config PRERAM_CBFS_CACHE_SIZE
 104         default 0x0
 105
 106 config ENABLE_BUILTIN_COM1
 107         bool "Enable builtin COM1 Serial Port"
 108         default n
 109         help
 110           The PMC has a legacy COM1 serial port. Choose this option to
 111           configure the pads and enable it. This serial port can be used for
 112           the debug console.
 113
 114 config DISABLE_HPET
 115         bool "Disable the HPET device"
 116         default n
 117         help
 118          Enable this to disable the HPET support
 119          Solves the Linux MP-BIOS bug timer not connected.
 120
 121 config HPET_MIN_TICKS
 122         default 0x80
 123
 124 config USE_GOOGLE_FSP
 125         bool
 126         help
 127          Select this to use Google's custom Braswell FSP header/binary
 128          instead of the public release on Github. Only google/cyan
 129          variants require this; all other boards should use the public release.
 130
 131 config FSP_HEADER_PATH
 132         string
 133         default "\$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP
 134         default "3rdparty/fsp/BraswellFspBinPkg/Include/"
 135         help
 136          Location of FSP header file FspUpdVpd.h
 137
 138 endif