1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef DPTF_CPU_PASSIVE
4 #define DPTF_CPU_PASSIVE 80
7 #ifndef DPTF_CPU_CRITICAL
8 #define DPTF_CPU_CRITICAL 90
11 #ifndef DPTF_CPU_ACTIVE_AC0
12 #define DPTF_CPU_ACTIVE_AC0 90
15 #ifndef DPTF_CPU_ACTIVE_AC1
16 #define DPTF_CPU_ACTIVE_AC1 80
19 #ifndef DPTF_CPU_ACTIVE_AC2
20 #define DPTF_CPU_ACTIVE_AC2 70
23 #ifndef DPTF_CPU_ACTIVE_AC3
24 #define DPTF_CPU_ACTIVE_AC3 60
27 #ifndef DPTF_CPU_ACTIVE_AC4
28 #define DPTF_CPU_ACTIVE_AC4 50
31 External (\_SB.CP00._TSS, MethodObj)
32 External (\_SB.CP00._TPC, MethodObj)
33 External (\_SB.CP00._PTC, PkgObj)
34 External (\_SB.CP00._TSD, PkgObj)
35 External (\_SB.CP00._PSS, MethodObj)
39 Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */
51 * Processor Throttling Controls
56 If (CondRefOf (\_SB.CP00._TSS)) {
57 Return (\_SB.CP00._TSS)
61 Package () { 0, 0, 0, 0, 0 }
68 If (CondRefOf (\_SB.CP00._TPC)) {
69 Return (\_SB.CP00._TPC)
77 If (CondRefOf (\_SB.CP00._PTC)) {
78 Return (\_SB.CP00._PTC)
90 If (CondRefOf (\_SB.CP00._TSD)) {
91 Return (\_SB.CP00._TSD)
95 Package () { 5, 0, 0, 0, 0 }
102 If (CondRefOf (\_SB.CP00._TSS)) {
103 Local0 = SizeOf (\_SB.CP00._TSS ())
112 * Processor Performance Control
124 /* Notify OS to re-read _PPC limit on each CPU */
130 If (CondRefOf (\_SB.CP00._PSS)) {
131 Return (\_SB.CP00._PSS)
135 Package () { 0, 0, 0, 0, 0, 0 }
142 /* Check for mainboard specific _PDL override */
143 If (CondRefOf (\_SB.MPDL)) {
145 } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
146 Local0 = SizeOf (\_SB.CP00._PSS ())
154 /* Return PPCC table defined by mainboard */
162 Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
167 Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
172 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
177 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
182 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
187 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
192 Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))