src/soc/intel/braswell/northcluster.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpigen.h>
   5 #include <cbmem.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <cpu/x86/lapic_def.h>
  11 #include <fsp/util.h>
  12 #include <soc/iomap.h>
  13 #include <soc/iosf.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/ramstage.h>
  16 #include <stddef.h>
  17
  18 /*
  19  * Host Memory Map:
  20  *
  21  * +--------------------------+ BMBOUND_HI
  22  * |     Usable DRAM          |
  23  * +--------------------------+ 4GiB
  24  * |     PCI Address Space    |
  25  * +--------------------------+ BMBOUND
  26  * |     TPM                  |
  27  * +--------------------------+ IMR2
  28  * |     TXE                  |
  29  * +--------------------------+ IMR1
  30  * |     iGD                  |
  31  * +--------------------------+
  32  * |     GTT                  |
  33  * +--------------------------+ SMMRRH, IRM0
  34  * |     TSEG                 |
  35  * +--------------------------+ SMMRRL
  36  * |     Usable DRAM          |
  37  * +--------------------------+ 0
  38  *
  39  * Note that there are really only a few regions that need to enumerated w.r.t.
  40  * coreboot's resource model:
  41  *
  42  * +--------------------------+ BMBOUND_HI
  43  * |     Cacheable/Usable     |
  44  * +--------------------------+ 4GiB
  45  *
  46  * +--------------------------+ BMBOUND
  47  * |    Uncacheable/Reserved  |
  48  * +--------------------------+ SMMRRH
  49  * |    Cacheable/Reserved    |
  50  * +--------------------------+ SMMRRL
  51  * |     Cacheable/Usable     |
  52  * +--------------------------+ 0
  53  */
  54 uint32_t nc_read_top_of_low_memory(void)
  55 {
  56         static uint32_t tolm;
  57
  58         if (tolm)
  59                 return tolm;
  60
  61         tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
  62
  63         return tolm;
  64 }
  65
  66 static void nc_read_resources(struct device *dev)
  67 {
  68         uint64_t mmconf;
  69         uint64_t bmbound;
  70         uint64_t bmbound_hi;
  71         uintptr_t smm_base;
  72         size_t smm_size;
  73         uint64_t tseg_base;
  74         uint64_t tseg_top;
  75         uint64_t fsp_res_base;
  76         void *fsp_reserved_memory_area;
  77         int index = 0;
  78
  79         /* Read standard PCI resources. */
  80         pci_dev_read_resources(dev);
  81
  82         /* Determine TSEG data */
  83         smm_region(&smm_base, &smm_size);
  84         tseg_base = smm_base;
  85         tseg_top = tseg_base + smm_size;
  86
  87         /* Determine the base of the FSP reserved memory */
  88         fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
  89         if (fsp_reserved_memory_area) {
  90                 fsp_res_base = (uintptr_t)fsp_reserved_memory_area;
  91         } else {
  92                 /* If no FSP reserved area */
  93                 fsp_res_base = tseg_base;
  94         }
  95
  96         /* PCIe memory-mapped config space access - 256 MiB. */
  97         mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
  98         mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB);
  99
 100         /* 0 -> 0xa0000 */
 101         ram_from_to(dev, index++, 0, 0xa0000);
 102
 103         /* High memory -> fsp_res_base - cacheable and usable */
 104         ram_from_to(dev, index++, 1 * MiB, fsp_res_base);
 105
 106         /* fsp_res_base -> tseg_top - Reserved */
 107         reserved_ram_from_to(dev, index++, fsp_res_base, tseg_top);
 108
 109         /* TSEG TOP -> bmbound is memory backed mmio. */
 110         bmbound = nc_read_top_of_low_memory();
 111         mmio_from_to(dev, index++, tseg_top, bmbound);
 112
 113         /*
 114          * The BMBOUND_HI register matches register bits of 31:24 with address
 115          * bits of 35:28. Therefore, shift register to align properly.
 116          */
 117         bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
 118         bmbound_hi <<= 4;
 119         upper_ram_end(dev, index++, bmbound_hi);
 120
 121         /*
 122          * Reserve everything between A segment and 1MB:
 123          *
 124          * 0xa0000 - 0xbffff: legacy VGA
 125          * 0xc0000 - 0xfffff: RAM
 126          */
 127         mmio_from_to(dev, index++, 0xa0000, 0xc0000);
 128         reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
 129
 130         /*
 131          * Reserve local APIC
 132          */
 133         mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 1 * MiB);
 134 }
 135
 136 static void nc_generate_ssdt(const struct device *dev)
 137 {
 138         generate_cpu_entries(dev);
 139
 140         acpigen_write_scope("\\");
 141         acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory());
 142         acpigen_pop_len();
 143 }
 144
 145 static struct device_operations nc_ops = {
 146         .read_resources = nc_read_resources,
 147         .acpi_fill_ssdt = nc_generate_ssdt,
 148         .ops_pci        = &soc_pci_ops,
 149 };
 150
 151 static const struct pci_driver nc_driver __pci_driver = {
 152         .ops    = &nc_ops,
 153         .vendor = PCI_VID_INTEL,
 154         .device = SOC_DEVID,
 155 };