src/soc/intel/braswell/southcluster.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <acpi/acpi.h>
   6 #include <arch/ioapic.h>
   7 #include <bootstate.h>
   8 #include "chip.h"
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci.h>
  12 #include <device/pci_ids.h>
  13 #include <intelblocks/lpc_lib.h>
  14 #include <pc80/isa-dma.h>
  15 #include <pc80/i8254.h>
  16 #include <pc80/i8259.h>
  17 #include <soc/acpi.h>
  18 #include <soc/iomap.h>
  19 #include <soc/irq.h>
  20 #include <soc/lpc.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/pm.h>
  23 #include <soc/ramstage.h>
  24 #include <soc/spi.h>
  25 #include <spi-generic.h>
  26 #include <stdint.h>
  27 #include <southbridge/intel/common/spi.h>
  28
  29 static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
  30 {
  31         u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xf);
  32
  33         switch (mode) {
  34         case SERIRQ_CONTINUOUS:
  35                 break;
  36
  37         case SERIRQ_OFF:
  38                 write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & ~SIRQEN);
  39                 break;
  40
  41         case SERIRQ_QUIET:
  42         default:
  43                 write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE);
  44                 break;
  45         }
  46 }
  47
  48 static void sc_add_mmio_resources(struct device *dev)
  49 {
  50         mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
  51         mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
  52         mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
  53         mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
  54         mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
  55         mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
  56         mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
  57         mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
  58         mmio_range(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1,
  59                    CONFIG_COREBOOT_ROMSIZE_KB * KiB);   /* BIOS ROM */
  60
  61         mmio_range(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
  62 }
  63
  64 /* Default IO range claimed by the LPC device. The upper bound is exclusive. */
  65 #define LPC_DEFAULT_IO_RANGE_LOWER 0
  66 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
  67
  68 static void sc_enable_serial_irqs(struct device *dev)
  69 {
  70         u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
  71
  72         printk(BIOS_SPEW, "Enable serial irq\n");
  73         write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) | SIRQEN);
  74         write8(ilb_base + SCNT, read8(ilb_base + SCNT) | SCNT_MODE);
  75 }
  76
  77 /*
  78  * Write PCI config space IRQ assignments. PCI devices have the INT_LINE (0x3c) and INT_PIN
  79  * (0x3d) registers which report interrupt routing information to operating systems and drivers.
  80  * The INT_PIN register is generally read only and reports which interrupt pin A - D it uses.
  81  * The INT_LINE register is configurable and reports which IRQ (generally the PIC IRQs 1 - 15)
  82  * it will use. This needs to take interrupt pin swizzling on devices that are downstream on
  83  * a PCI bridge into account.
  84  *
  85  * This function will loop through all enabled PCI devices and program the INT_LINE register
  86  * with the correct PIC IRQ number for the INT_PIN that it uses.  It then configures each
  87  * interrupt in the PIC to be level triggered.
  88  */
  89 static void write_pci_config_irqs(void)
  90 {
  91         struct device *irq_dev;
  92         struct device *targ_dev;
  93         uint8_t int_line = 0;
  94         uint8_t original_int_pin = 0;
  95         uint8_t new_int_pin = 0;
  96         uint16_t current_bdf = 0;
  97         uint16_t parent_bdf = 0;
  98         uint8_t pirq = 0;
  99         uint8_t device_num = 0;
 100         const struct soc_irq_route *ir = &global_soc_irq_route;
 101
 102         if (ir == NULL) {
 103                 printk(BIOS_WARNING, "Can't write PCI IRQ assignments "
 104                         "because 'global_braswell_irq_route' structure does not exist\n");
 105                 return;
 106         }
 107
 108         /*
 109          * Loop through all enabled devices and program their INT_LINE, INT_PIN registers from
 110          * values taken from the Interrupt Route registers in the ILB
 111          */
 112         printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n");
 113         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 114                 if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 115                         (!irq_dev->enabled))
 116                         continue;
 117
 118                 current_bdf = irq_dev->path.pci.devfn |
 119                         irq_dev->upstream->secondary << 8;
 120
 121                 /*
 122                  * Step 1: Get the INT_PIN and device structure to look for
 123                  * in the pirq_data table defined in the mainboard directory.
 124                  */
 125                 targ_dev = NULL;
 126                 new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
 127                 if (targ_dev == NULL || new_int_pin < 1)
 128                         continue;
 129
 130                 /* Get the original INT_PIN for record keeping */
 131                 original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 132
 133                 parent_bdf = targ_dev->path.pci.devfn
 134                         | targ_dev->upstream->secondary << 8;
 135                 device_num = PCI_SLOT(parent_bdf);
 136
 137                 if (ir->pcidev[device_num] == 0) {
 138                         printk(BIOS_WARNING, "PCI Device %d does not have an IRQ entry, "
 139                                 "skipping it\n", device_num);
 140                         continue;
 141                 }
 142
 143                 /* Find the PIRQ that is attached to the INT_PIN  */
 144                 pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4))
 145                                         & 0x7;
 146
 147                 /* Get the INT_LINE this device/function will use */
 148                 int_line = ir->pic[pirq];
 149
 150                 if (int_line != PIRQ_PIC_IRQDISABLE) {
 151                         /* Set this IRQ to level triggered */
 152                         i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
 153
 154                         /* Set the Interrupt Line register */
 155                         pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 156                 } else {
 157                         /* Set the Interrupt line register as 'unknown' or 'unused' */
 158                         pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, PIRQ_PIC_UNKNOWN_UNUSED);
 159                 }
 160
 161                 printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", original_int_pin,
 162                         pin_to_str(original_int_pin));
 163
 164                 if (parent_bdf != current_bdf)
 165                         printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", new_int_pin,
 166                                 pin_to_str(new_int_pin));
 167
 168                 printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n\tINT_LINE\t: 0x%X (IRQ %d)\n",
 169                         'A' + pirq, int_line, int_line);
 170         }
 171         printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PIRQ assignments\n");
 172 }
 173
 174 static inline int io_range_in_default(int base, int size)
 175 {
 176         /* Does it start above the range? */
 177         if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
 178                 return 0;
 179
 180         /* Is it entirely contained? */
 181         if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
 182                 return 1;
 183
 184         /* This will return not in range for partial overlaps */
 185         return 0;
 186 }
 187
 188 /*
 189  * Note: this function assumes there is no overlap with the default LPC device's
 190  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
 191  */
 192 static void sc_add_io_resource(struct device *dev, int base, int size, int index)
 193 {
 194         struct resource *res;
 195
 196         if (io_range_in_default(base, size))
 197                 return;
 198
 199         res = new_resource(dev, index);
 200         res->base = base;
 201         res->size = size;
 202         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 203 }
 204
 205 static void sc_add_io_resources(struct device *dev)
 206 {
 207         struct resource *res;
 208
 209         /* Add the default claimed IO range for the LPC device. */
 210         res = new_resource(dev, 0);
 211         res->base = LPC_DEFAULT_IO_RANGE_LOWER;
 212         res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
 213         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 214
 215         /* GPIO */
 216         sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE);
 217
 218         /* ACPI */
 219         sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
 220 }
 221
 222 static void sc_read_resources(struct device *dev)
 223 {
 224         /* Get the normal PCI resources of this device. */
 225         pci_dev_read_resources(dev);
 226
 227         /* Add non-standard MMIO resources. */
 228         sc_add_mmio_resources(dev);
 229
 230         /* Add IO resources. */
 231         sc_add_io_resources(dev);
 232 }
 233
 234 static void sc_init(struct device *dev)
 235 {
 236         int i;
 237         const unsigned long ilb_base = ILB_BASE_ADDRESS;
 238         const unsigned long pr_base  = ILB_BASE_ADDRESS + 0x08;
 239         const unsigned long ir_base  = ILB_BASE_ADDRESS + 0x20;
 240
 241         void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1);
 242         const struct soc_irq_route *ir = &global_soc_irq_route;
 243         struct soc_intel_braswell_config *config = config_of(dev);
 244
 245         /* Set the value for PCI command register. */
 246         pci_write_config16(dev, PCI_COMMAND,
 247                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 248
 249         /* Use IRQ9 for SCI Interrupt */
 250         write32((void *)(ilb_base + ACTL), 0);
 251
 252         isa_dma_init();
 253
 254         sc_enable_serial_irqs(dev);
 255
 256         /* Set up the PIRQ PIC routing based on static config. */
 257         for (i = 0; i < NUM_PIRQS; i++)
 258                 write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]);
 259
 260         /* Set up the per device PIRQ routing base on static config. */
 261         for (i = 0; i < NUM_IR_DEVS; i++)
 262                 write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]);
 263
 264         /* Interrupt 9 should be level triggered (SCI) */
 265         i8259_configure_irq_trigger(9, 1);
 266
 267         for (i = 0; i < NUM_PIRQS; i++) {
 268                 if (ir->pic[i])
 269                         i8259_configure_irq_trigger(ir->pic[i], 1);
 270         }
 271
 272         if (config->disable_slp_x_stretch_sus_fail) {
 273                 printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
 274                 write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
 275
 276         } else {
 277                 write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 278         }
 279
 280         /* Write IRQ assignments to PCI config space */
 281         write_pci_config_irqs();
 282
 283         /* Initialize i8259 pic */
 284         setup_i8259();
 285
 286         /* Initialize i8254 timers */
 287         setup_i8254();
 288
 289         sc_set_serial_irqs_mode(dev, config->serirq_mode);
 290 }
 291
 292 /*
 293  * Common code for the south cluster devices.
 294  */
 295
 296 /* Set bit in function disable register to hide this device. */
 297 static void sc_disable_devfn(struct device *dev)
 298 {
 299         void *func_dis  = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
 300         void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
 301         uint32_t mask  = 0;
 302         uint32_t mask2 = 0;
 303
 304 #define SET_DIS_MASK(name_) \
 305         case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
 306                 mask |= name_ ## _DIS
 307
 308 #define SET_DIS_MASK2(name_) \
 309         case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
 310                 mask2 |= name_ ## _DIS
 311
 312         switch (dev->path.pci.devfn) {
 313         SET_DIS_MASK(SDIO);
 314                 break;
 315         SET_DIS_MASK(SD);
 316                 break;
 317         SET_DIS_MASK(SATA);
 318                 break;
 319         SET_DIS_MASK(XHCI);
 320                 /* Disable super speed PHY when XHCI is not available. */
 321                 mask2 |= USH_SS_PHY_DIS;
 322                 break;
 323         SET_DIS_MASK(LPE);
 324                 break;
 325         SET_DIS_MASK(MMC);
 326                 break;
 327         SET_DIS_MASK(SIO_DMA1);
 328                 break;
 329         SET_DIS_MASK(I2C1);
 330                 break;
 331         SET_DIS_MASK(I2C2);
 332                 break;
 333         SET_DIS_MASK(I2C3);
 334                 break;
 335         SET_DIS_MASK(I2C4);
 336                 break;
 337         SET_DIS_MASK(I2C5);
 338                 break;
 339         SET_DIS_MASK(I2C6);
 340                 break;
 341         SET_DIS_MASK(I2C7);
 342                 break;
 343         SET_DIS_MASK(TXE);
 344                 break;
 345         SET_DIS_MASK(HDA);
 346                 break;
 347         SET_DIS_MASK(PCIE_PORT1);
 348                 break;
 349         SET_DIS_MASK(PCIE_PORT2);
 350                 break;
 351         SET_DIS_MASK(PCIE_PORT3);
 352                 break;
 353         SET_DIS_MASK(PCIE_PORT4);
 354                 break;
 355         SET_DIS_MASK(SIO_DMA2);
 356                 break;
 357         SET_DIS_MASK(PWM1);
 358                 break;
 359         SET_DIS_MASK(PWM2);
 360                 break;
 361         SET_DIS_MASK(HSUART1);
 362                 break;
 363         SET_DIS_MASK(HSUART2);
 364                 break;
 365         SET_DIS_MASK(SPI);
 366                 break;
 367         SET_DIS_MASK2(SMBUS);
 368                 break;
 369         }
 370
 371         if (mask != 0) {
 372                 write32(func_dis, read32(func_dis) | mask);
 373                 /* Ensure posted write hits */
 374                 read32(func_dis);
 375         }
 376
 377         if (mask2 != 0) {
 378                 write32(func_dis2, read32(func_dis2) | mask2);
 379                 /* Ensure posted write hits */
 380                 read32(func_dis2);
 381         }
 382 }
 383
 384 static inline void set_d3hot_bits(struct device *dev, int offset)
 385 {
 386         uint32_t reg8;
 387         printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
 388         reg8 = pci_read_config8(dev, offset + 4);
 389         reg8 |= 0x3;
 390         pci_write_config8(dev, offset + 4, reg8);
 391 }
 392
 393 /*
 394  * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into
 395  * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio.
 396  */
 397 static void hda_work_around(struct device *dev)
 398 {
 399         void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
 400
 401         /* Need to set magic register 0x43 to 0xd7 in config space. */
 402         pci_write_config8(dev, 0x43, 0xd7);
 403
 404         /*
 405          * Need to set bit 0 of GCTL to take the device out of reset.
 406          * However, that requires setting up the 64-bit BAR.
 407          */
 408         pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
 409         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
 410         pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 411         write32(gctl, read32(gctl) | 0x1);
 412         pci_write_config16(dev, PCI_COMMAND, 0);
 413         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
 414 }
 415
 416 static int place_device_in_d3hot(struct device *dev)
 417 {
 418         unsigned int offset;
 419
 420         /*
 421          * Parts of the HDA block are used for LPE audio as well.
 422          * Therefore assume the HDA will never be put into D3Hot.
 423          */
 424         if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) {
 425                 hda_work_around(dev);
 426                 return 0;
 427         }
 428
 429         offset = pci_find_capability(dev, PCI_CAP_ID_PM);
 430
 431         if (offset != 0) {
 432                 set_d3hot_bits(dev, offset);
 433                 return 0;
 434         }
 435
 436         /*
 437          * For some reason some of the devices don't have the capability pointer set correctly.
 438          * Work around this by hard coding the offset.
 439          */
 440 #define DEV_CASE(name_) \
 441         case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
 442
 443         switch (dev->path.pci.devfn) {
 444         DEV_CASE(SDIO) :
 445         DEV_CASE(SD) :
 446         DEV_CASE(MMC) :
 447         DEV_CASE(LPE) :
 448         DEV_CASE(SIO_DMA1) :
 449         DEV_CASE(I2C1) :
 450         DEV_CASE(I2C2) :
 451         DEV_CASE(I2C3) :
 452         DEV_CASE(I2C4) :
 453         DEV_CASE(I2C5) :
 454         DEV_CASE(I2C6) :
 455         DEV_CASE(I2C7) :
 456         DEV_CASE(SIO_DMA2) :
 457         DEV_CASE(PWM1) :
 458         DEV_CASE(PWM2) :
 459         DEV_CASE(HSUART1) :
 460         DEV_CASE(HSUART2) :
 461         DEV_CASE(SPI) :
 462                 offset = 0x80;
 463                 break;
 464         DEV_CASE(SATA) :
 465         DEV_CASE(XHCI) :
 466                 offset = 0x70;
 467                 break;
 468         DEV_CASE(HDA) :
 469         DEV_CASE(SMBUS) :
 470                 offset = 0x50;
 471                 break;
 472         DEV_CASE(TXE) :
 473                 /* TXE cannot be placed in D3Hot. */
 474                 return 0;
 475         DEV_CASE(PCIE_PORT1) :
 476         DEV_CASE(PCIE_PORT2) :
 477         DEV_CASE(PCIE_PORT3) :
 478         DEV_CASE(PCIE_PORT4) :
 479                 offset = 0xa0;
 480                 break;
 481         }
 482
 483         if (offset != 0) {
 484                 set_d3hot_bits(dev, offset);
 485                 return 0;
 486         }
 487
 488         return -1;
 489 }
 490
 491 /* Common PCI device function disable. */
 492 void southcluster_enable_dev(struct device *dev)
 493 {
 494         uint16_t reg16;
 495
 496         if (!dev->enabled) {
 497                 int slot = PCI_SLOT(dev->path.pci.devfn);
 498                 int func = PCI_FUNC(dev->path.pci.devfn);
 499                 printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
 500                        dev_path(dev), slot, func);
 501
 502                 /* Ensure memory, io, and bus master are all disabled */
 503                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 504                 reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 505                 pci_write_config16(dev, PCI_COMMAND, reg16);
 506
 507                 /* Place device in D3Hot */
 508                 if (place_device_in_d3hot(dev) < 0) {
 509                         printk(BIOS_WARNING,
 510                                "Could not place %02x.%01x into D3Hot. "
 511                                "Keeping device visible.\n", slot, func);
 512                         return;
 513                 }
 514                 /* Disable this device if possible */
 515                 sc_disable_devfn(dev);
 516         } else {
 517                 /* Enable SERR */
 518                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 519         }
 520 }
 521
 522 static struct device_operations device_ops = {
 523         .read_resources                 = sc_read_resources,
 524         .set_resources                  = pci_dev_set_resources,
 525         .write_acpi_tables              = southcluster_write_acpi_tables,
 526         .init                           = sc_init,
 527         .enable                         = southcluster_enable_dev,
 528         .scan_bus                       = scan_static_bus,
 529         .ops_pci                        = &soc_pci_ops,
 530 };
 531
 532 static const struct pci_driver southcluster __pci_driver = {
 533         .ops            = &device_ops,
 534         .vendor         = PCI_VID_INTEL,
 535         .device         = LPC_DEVID,
 536 };
 537
 538 static void finalize_chipset(void *unused)
 539 {
 540         void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
 541         void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS);
 542         void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
 543         void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
 544         uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
 545
 546         struct vscc_config cfg;
 547
 548         /* Set the lock enable on the BIOS control register */
 549         write32(bcr, read32(bcr) | BCR_LE);
 550
 551         /* Set BIOS lock down bit controlling boot block size and swapping */
 552         write32(gcs, read32(gcs) | BILD);
 553
 554         /* Lock sleep stretching policy and set SMI lock */
 555         write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
 556
 557         /*  Set the CF9 lock */
 558         write32(etr, read32(etr) | CF9LOCK);
 559
 560         spi_finalize_ops();
 561         write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
 562
 563         if (mainboard_get_spi_vscc_config(&cfg) < 0) {
 564                 printk(BIOS_DEBUG, "No SPI VSCC configuration.\n");
 565         } else {
 566                 write32(spi + UVSCC, cfg.uvscc);
 567                 write32(spi + LVSCC, cfg.lvscc | VCL);
 568         }
 569 }
 570
 571 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL);