src/soc/intel/denverton_ns/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/romstage.h>
   4 #include <cbmem.h>
   5 #include <cpu/x86/mtrr.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/device.h>
   8 #include <device/pci_def.h>
   9 #include <device/pci_ops.h>
  10 #include <soc/pci_devs.h>
  11 #include <soc/systemagent.h>
  12
  13 /* Returns base of requested region encoded in the system agent. */
  14 static inline uintptr_t system_agent_region_base(size_t reg)
  15 {
  16 #if defined(__SIMPLE_DEVICE__)
  17         pci_devfn_t dev = SA_DEV_ROOT;
  18 #else
  19         struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  20 #endif
  21         /* All regions concerned for have 1 MiB alignment. */
  22         return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
  23 }
  24
  25 static inline uintptr_t smm_region_start(void)
  26 {
  27         return system_agent_region_base(TSEGMB);
  28 }
  29
  30 static inline size_t smm_region_size(void)
  31 {
  32         return system_agent_region_base(TOLUD) - smm_region_start();
  33 }
  34
  35 void smm_region(uintptr_t *start, size_t *size)
  36 {
  37         *start = smm_region_start();
  38         *size = smm_region_size();
  39 }
  40
  41 void fill_postcar_frame(struct postcar_frame *pcf)
  42 {
  43         /*
  44          * We need to make sure ramstage will be run cached. At this point exact
  45          * location of ramstage in cbmem is not known. Instruct postcar to cache
  46          * 16 megs under cbmem top which is a safe bet to cover ramstage.
  47          */
  48         const uintptr_t top_of_ram = cbmem_top();
  49         postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
  50                                MTRR_TYPE_WRBACK);
  51
  52         /* Cache the TSEG region */
  53         postcar_enable_tseg_cache(pcf);
  54 }