src/soc/intel/jasperlake/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_JASPERLAKE
   4         bool
   5         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   6         select ARCH_X86
   7         select BOOT_DEVICE_SUPPORTS_WRITES
   8         select CACHE_MRC_SETTINGS
   9         select CPU_INTEL_COMMON
  10         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  11         select CPU_SUPPORTS_PM_TIMER_EMULATION
  12         select COS_MAPPED_TO_MSB
  13         select DISPLAY_FSP_VERSION_INFO_2
  14         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  15         select FSP_COMPRESS_FSP_S_LZ4
  16         select FSP_M_XIP
  17         select GENERIC_GPIO_LIB
  18         select HAVE_DPTF_EISA_HID
  19         select HAVE_FSP_GOP
  20         select INTEL_DESCRIPTOR_MODE_CAPABLE
  21         select HAVE_SMI_HANDLER
  22         select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
  23         select IDT_IN_EVERY_STAGE
  24         select INTEL_CAR_NEM_ENHANCED
  25         select INTEL_GMA_ACPI
  26         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  27         select MP_SERVICES_PPI_V1
  28         select MRC_SETTINGS_PROTECT
  29         select PARALLEL_MP_AP_WORK
  30         select PLATFORM_USES_FSP2_2
  31         select PMC_GLOBAL_RESET_ENABLE_LOCK
  32         select SOC_INTEL_COMMON
  33         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  34         select SOC_INTEL_COMMON_BLOCK
  35         select SOC_INTEL_COMMON_BLOCK_ACPI
  36         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  37         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  38         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  39         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  40         select SOC_INTEL_COMMON_BLOCK_CAR
  41         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  42         select SOC_INTEL_COMMON_BLOCK_CNVI
  43         select SOC_INTEL_COMMON_BLOCK_CPU
  44         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  45         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  46         select SOC_INTEL_COMMON_BLOCK_DTT
  47         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  48         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  49         select SOC_INTEL_COMMON_BLOCK_HDA
  50         select SOC_INTEL_COMMON_BLOCK_ME_SPEC_13
  51         select SOC_INTEL_COMMON_BLOCK_SA
  52         select SOC_INTEL_COMMON_BLOCK_SCS
  53         select SOC_INTEL_COMMON_BLOCK_SMM
  54         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  55         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  56         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  57         select SOC_INTEL_COMMON_FSP_RESET
  58         select SOC_INTEL_COMMON_PCH_CLIENT
  59         select SOC_INTEL_COMMON_RESET
  60         select SOC_INTEL_CSE_SEND_EOP_LATE
  61         select SOC_INTEL_CSE_SET_EOP
  62         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  63         select SSE2
  64         select SUPPORT_CPU_UCODE_IN_CBFS
  65         select TSC_MONOTONIC_TIMER
  66         select UDELAY_TSC
  67         select UDK_202005_BINDING
  68         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  69         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  70         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  71         select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
  72         help
  73           Intel Jasperlake support
  74
  75 if SOC_INTEL_JASPERLAKE
  76
  77 config DCACHE_RAM_BASE
  78         default 0xfef00000
  79
  80 config DCACHE_RAM_SIZE
  81         default 0x80000
  82         help
  83           The size of the cache-as-ram region required during bootblock
  84           and/or romstage.
  85
  86 config DCACHE_BSP_STACK_SIZE
  87         hex
  88         default 0x30400
  89         help
  90           The amount of anticipated stack usage in CAR by bootblock and
  91           other stages. In the case of FSP_USES_CB_STACK default value
  92           will be sum of FSP-M stack requirement(192 KiB) and CB romstage
  93           stack requirement(~1KiB).
  94
  95 config FSP_TEMP_RAM_SIZE
  96         hex
  97         default 0x20000
  98         help
  99           The amount of anticipated heap usage in CAR by FSP.
 100           Refer to Platform FSP integration guide document to know
 101           the exact FSP requirement for Heap setup.
 102
 103 config IFD_CHIPSET
 104         string
 105         default "jsl"
 106
 107 config IED_REGION_SIZE
 108         hex
 109         default 0x400000
 110
 111 config MAX_ROOT_PORTS
 112         int
 113         default 8
 114
 115 config MAX_PCIE_CLOCK_SRC
 116         int
 117         default 6
 118
 119 config SMM_TSEG_SIZE
 120         hex
 121         default 0x800000
 122
 123 config SMM_RESERVED_SIZE
 124         hex
 125         default 0x200000
 126
 127 config PCR_BASE_ADDRESS
 128         hex
 129         default 0xfd000000
 130         help
 131           This option allows you to select MMIO Base Address of sideband bus.
 132
 133 config ECAM_MMCONF_BASE_ADDRESS
 134         default 0xc0000000
 135
 136 config CPU_BCLK_MHZ
 137         int
 138         default 100
 139
 140 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 141         int
 142         default 120
 143
 144 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 145         int
 146         default 133
 147
 148 config CPU_XTAL_HZ
 149         default 38400000
 150
 151 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 152         int
 153         default 3
 154
 155 config SOC_INTEL_I2C_DEV_MAX
 156         int
 157         default 6
 158
 159 config SOC_INTEL_UART_DEV_MAX
 160         int
 161         default 3
 162
 163 config CONSOLE_UART_BASE_ADDRESS
 164         hex
 165         default 0xfe032000
 166         depends on INTEL_LPSS_UART_FOR_CONSOLE
 167
 168 # Clock divider parameters for 115200 baud rate
 169 # Baudrate = (UART source clock * M) /(N *16)
 170 # JSL UART source clock: 100MHz
 171 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 172         hex
 173         default 0x30
 174
 175 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 176         hex
 177         default 0xc35
 178
 179 config VBOOT
 180         select VBOOT_MUST_REQUEST_DISPLAY
 181         select VBOOT_STARTS_IN_BOOTBLOCK
 182         select VBOOT_VBNV_CMOS
 183         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 184
 185 config CBFS_SIZE
 186         default 0x200000
 187
 188 config FSP_HEADER_PATH
 189         default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"
 190
 191 config FSP_FD_PATH
 192         default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
 193
 194 config PRERAM_CBMEM_CONSOLE_SIZE
 195         hex
 196         default 0x1400
 197
 198 config INTEL_GMA_BCLV_OFFSET
 199         default 0xc8258
 200
 201 config INTEL_GMA_BCLV_WIDTH
 202         default 32
 203
 204 config INTEL_GMA_BCLM_OFFSET
 205         default 0xc8254
 206
 207 config INTEL_GMA_BCLM_WIDTH
 208         default 32
 209 endif