src/soc/intel/jasperlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <device/device.h>
   8 #include <device/mmio.h>
   9 #include <arch/smp/mpspec.h>
  10 #include <console/console.h>
  11 #include <device/pci_ops.h>
  12 #include <intelblocks/cpulib.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/acpi.h>
  15 #include <soc/cpu.h>
  16 #include <soc/iomap.h>
  17 #include <soc/nvs.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22 #include <static.h>
  23
  24 /*
  25  * List of supported C-states in this processor.
  26  */
  27 enum {
  28         C_STATE_C0,             /* 0 */
  29         C_STATE_C1,             /* 1 */
  30         C_STATE_C1E,            /* 2 */
  31         C_STATE_C6_SHORT_LAT,   /* 3 */
  32         C_STATE_C6_LONG_LAT,    /* 4 */
  33         C_STATE_C7_SHORT_LAT,   /* 5 */
  34         C_STATE_C7_LONG_LAT,    /* 6 */
  35         C_STATE_C7S_SHORT_LAT,  /* 7 */
  36         C_STATE_C7S_LONG_LAT,   /* 8 */
  37         C_STATE_C8,             /* 9 */
  38         C_STATE_C9,             /* 10 */
  39         C_STATE_C10,            /* 11 */
  40         NUM_C_STATES
  41 };
  42
  43 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  44         [C_STATE_C0] = {},
  45         [C_STATE_C1] = {
  46                 .latency = C1_LATENCY,
  47                 .power = C1_POWER,
  48                 .resource = MWAIT_RES(0, 0),
  49         },
  50         [C_STATE_C1E] = {
  51                 .latency = C1_LATENCY,
  52                 .power = C1_POWER,
  53                 .resource = MWAIT_RES(0, 1),
  54         },
  55         [C_STATE_C6_SHORT_LAT] = {
  56                 .latency = C6_LATENCY,
  57                 .power = C6_POWER,
  58                 .resource = MWAIT_RES(2, 0),
  59         },
  60         [C_STATE_C6_LONG_LAT] = {
  61                 .latency = C6_LATENCY,
  62                 .power = C6_POWER,
  63                 .resource = MWAIT_RES(2, 1),
  64         },
  65         [C_STATE_C7_SHORT_LAT] = {
  66                 .latency = C7_LATENCY,
  67                 .power = C7_POWER,
  68                 .resource = MWAIT_RES(3, 0),
  69         },
  70         [C_STATE_C7_LONG_LAT] = {
  71                 .latency = C7_LATENCY,
  72                 .power = C7_POWER,
  73                 .resource = MWAIT_RES(3, 1),
  74         },
  75         [C_STATE_C7S_SHORT_LAT] = {
  76                 .latency = C7_LATENCY,
  77                 .power = C7_POWER,
  78                 .resource = MWAIT_RES(3, 2),
  79         },
  80         [C_STATE_C7S_LONG_LAT] = {
  81                 .latency = C7_LATENCY,
  82                 .power = C7_POWER,
  83                 .resource = MWAIT_RES(3, 3),
  84         },
  85         [C_STATE_C8] = {
  86                 .latency = C8_LATENCY,
  87                 .power = C8_POWER,
  88                 .resource = MWAIT_RES(4, 0),
  89         },
  90         [C_STATE_C9] = {
  91                 .latency = C9_LATENCY,
  92                 .power = C9_POWER,
  93                 .resource = MWAIT_RES(5, 0),
  94         },
  95         [C_STATE_C10] = {
  96                 .latency = C10_LATENCY,
  97                 .power = C10_POWER,
  98                 .resource = MWAIT_RES(6, 0),
  99         },
 100 };
 101
 102 static int cstate_set_non_s0ix[] = {
 103         C_STATE_C1,
 104         C_STATE_C6_LONG_LAT,
 105         C_STATE_C7S_LONG_LAT
 106 };
 107
 108 static int cstate_set_s0ix[] = {
 109         C_STATE_C1,
 110         C_STATE_C7S_LONG_LAT,
 111         C_STATE_C10
 112 };
 113
 114 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 115 {
 116         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 117                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 118         int *set;
 119         int i;
 120
 121         config_t *config = config_of_soc();
 122
 123         int is_s0ix_enable = config->s0ix_enable;
 124
 125         if (is_s0ix_enable) {
 126                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 127                 set = cstate_set_s0ix;
 128         } else {
 129                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 130                 set = cstate_set_non_s0ix;
 131         }
 132
 133         for (i = 0; i < *entries; i++) {
 134                 map[i] = cstate_map[set[i]];
 135                 map[i].ctype = i + 1;
 136         }
 137         return map;
 138 }
 139
 140 void soc_power_states_generation(int core_id, int cores_per_package)
 141 {
 142         config_t *config = config_of_soc();
 143
 144         if (config->eist_enable)
 145                 /* Generate P-state tables */
 146                 generate_p_state_entries(core_id, cores_per_package);
 147 }
 148
 149 void soc_fill_fadt(acpi_fadt_t *fadt)
 150 {
 151         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 152
 153         config_t *config = config_of_soc();
 154
 155         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 156         fadt->pm_tmr_len = 4;
 157
 158         fill_fadt_extended_pm_io(fadt);
 159
 160         if (config->s0ix_enable)
 161                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 162 }
 163
 164 uint32_t soc_read_sci_irq_select(void)
 165 {
 166         return read32p(soc_read_pmc_base() + IRQ_REG);
 167 }
 168
 169 static unsigned long soc_fill_dmar(unsigned long current)
 170 {
 171         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 172         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 173
 174         if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
 175                 unsigned long tmp = current;
 176
 177                 current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
 178                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 179
 180                 acpi_dmar_drhd_fixup(tmp, current);
 181         }
 182
 183         uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 184         bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 185
 186         if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
 187                 unsigned long tmp = current;
 188
 189                 current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
 190                 current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
 191
 192                 acpi_dmar_drhd_fixup(tmp, current);
 193         }
 194
 195         uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 196         bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 197
 198         if (vtvc0bar && vtvc0en) {
 199                 const unsigned long tmp = current;
 200
 201                 current += acpi_create_dmar_drhd_4k(current,
 202                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 203                 current += acpi_create_dmar_ds_ioapic_from_hw(current,
 204                                 IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 205                                 V_P2SB_CFG_IBDF_FUNC);
 206                 current += acpi_create_dmar_ds_msi_hpet(current,
 207                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 208                                 V_P2SB_CFG_HBDF_FUNC);
 209
 210                 acpi_dmar_drhd_fixup(tmp, current);
 211         }
 212
 213         /* Add RMRR entry */
 214         const unsigned long tmp = current;
 215         current += acpi_create_dmar_rmrr(current, 0,
 216                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 217         current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 218         acpi_dmar_rmrr_fixup(tmp, current);
 219
 220         return current;
 221 }
 222
 223 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 224                                    struct acpi_rsdp *rsdp)
 225 {
 226         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 227
 228         /*
 229          * Create DMAR table only if we have VT-d capability and FSP does not override its
 230          * feature.
 231          */
 232         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 233             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 234                 return current;
 235
 236         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 237         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 238         current += dmar->header.length;
 239         current = acpi_align_current(current);
 240         acpi_add_table(rsdp, dmar);
 241
 242         return current;
 243 }
 244
 245 void soc_fill_gnvs(struct global_nvs *gnvs)
 246 {
 247         config_t *config = config_of_soc();
 248
 249         /* Enable DPTF based on mainboard configuration */
 250         gnvs->dpte = config->dptf_enable;
 251
 252         /* Set USB2/USB3 wake enable bitmaps. */
 253         gnvs->u2we = config->usb2_wake_enable_bitmap;
 254         gnvs->u3we = config->usb3_wake_enable_bitmap;
 255 }
 256
 257 int soc_madt_sci_irq_polarity(int sci)
 258 {
 259         return MP_IRQ_POLARITY_HIGH;
 260 }