src/soc/intel/jasperlake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_CHIP_H_
   4 #define _SOC_CHIP_H_
   5
   6 #include <device/pci_ids.h>
   7 #include <drivers/i2c/designware/dw_i2c.h>
   8 #include <gpio.h>
   9 #include <drivers/intel/gma/gma.h>
  10 #include <intelblocks/cfg.h>
  11 #include <intelblocks/gspi.h>
  12 #include <intelblocks/pcie_rp.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <intelblocks/xhci.h>
  15 #include <soc/gpe.h>
  16 #include <soc/pch.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/pcie_modphy.h>
  19 #include <soc/pmc.h>
  20 #include <soc/serialio.h>
  21 #include <soc/usb.h>
  22 #include <stdint.h>
  23 #include <stdbool.h>
  24
  25 #define MAX_HD_AUDIO_DMIC_LINKS 2
  26 #define MAX_HD_AUDIO_SNDW_LINKS 4
  27 #define MAX_HD_AUDIO_SSP_LINKS  6
  28
  29 /* Types of different SKUs */
  30 enum soc_intel_jasperlake_power_limits {
  31         JSL_N4500_6W_CORE,
  32         JSL_N6000_6W_CORE,
  33         JSL_N5100_6W_CORE,
  34         JSL_N4505_10W_CORE,
  35         JSL_N5105_10W_CORE,
  36         JSL_N6005_10W_CORE,
  37         JSL_POWER_LIMITS_COUNT
  38 };
  39
  40 /* TDP values for different SKUs */
  41 enum soc_intel_jasperlake_cpu_tdps {
  42         TDP_6W  = 6,
  43         TDP_10W = 10
  44 };
  45
  46 /* Mapping of different SKUs based on CPU ID and TDP values */
  47 static const struct {
  48         unsigned int pci_did;
  49         enum soc_intel_jasperlake_power_limits limits;
  50         enum soc_intel_jasperlake_cpu_tdps cpu_tdp;
  51 } cpuid_to_jsl[] = {
  52         { PCI_DID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W },
  53         { PCI_DID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W },
  54         { PCI_DID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W },
  55         { PCI_DID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W },
  56         { PCI_DID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W },
  57         { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W },
  58 };
  59
  60 struct soc_intel_jasperlake_config {
  61         /* Common struct containing soc config data required by common code */
  62         struct soc_intel_common_config common_soc_config;
  63
  64         /* Common struct containing power limits configuration information */
  65         struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT];
  66
  67         /* Gpio group routed to each dword of the GPE0 block. Values are
  68          * of the form PMC_GPP_[A:U] or GPD. */
  69         uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
  70         uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
  71         uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
  72
  73         /* Generic IO decode ranges */
  74         uint32_t gen1_dec;
  75         uint32_t gen2_dec;
  76         uint32_t gen3_dec;
  77         uint32_t gen4_dec;
  78
  79         /* Enable S0iX support */
  80         bool s0ix_enable;
  81         /* Enable DPTF support */
  82         bool dptf_enable;
  83
  84         /* Deep SX enable for both AC and DC */
  85         bool deep_s3_enable_ac;
  86         bool deep_s3_enable_dc;
  87         bool deep_s5_enable_ac;
  88         bool deep_s5_enable_dc;
  89
  90         /* Deep Sx Configuration
  91          *  DSX_EN_WAKE_PIN       - Enable WAKE# pin
  92          *  DSX_EN_LAN_WAKE_PIN   - Enable LAN_WAKE# pin
  93          *  DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
  94         uint32_t deep_sx_config;
  95
  96         /* TCC activation offset */
  97         uint32_t tcc_offset;
  98
  99         /* System Agent dynamic frequency support.
 100          * When enabled memory will be training at different frequencies.
 101          * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2
 102          * (high), 4:Enabled */
 103         enum {
 104                 SaGv_Disabled,
 105                 SaGv_FixedPoint0,
 106                 SaGv_FixedPoint1,
 107                 SaGv_FixedPoint2,
 108                 SaGv_Enabled,
 109         } SaGv;
 110
 111         /* Rank Margin Tool */
 112         bool RMT;
 113
 114         /* USB related */
 115         struct usb2_port_config usb2_ports[16];
 116         struct usb3_port_config usb3_ports[10];
 117         /* Wake Enable Bitmap for USB2 ports */
 118         uint16_t usb2_wake_enable_bitmap;
 119         /* Wake Enable Bitmap for USB3 ports */
 120         uint16_t usb3_wake_enable_bitmap;
 121
 122         /* Set the LFPS periodic sampling off time for USB3 Ports.
 123            Default value of PMCTRL_REG bits[7:4] is 9 which means periodic
 124            sampling off interval is 9ms, the range is from 0 to 15. */
 125         uint8_t xhci_lfps_sampling_offtime_ms;
 126
 127         /* SATA related */
 128         uint8_t SataMode;
 129         bool SataSalpSupport;
 130         bool SataPortsEnable[8];
 131         bool SataPortsDevSlp[8];
 132
 133         /* Audio related */
 134         bool PchHdaDspEnable;
 135         bool PchHdaAudioLinkHdaEnable;
 136         bool PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
 137         bool PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
 138         bool PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
 139         uint8_t PchHdaIDispLinkTmode;
 140         uint8_t PchHdaIDispLinkFrequency;
 141         bool PchHdaIDispCodecDisconnect;
 142
 143         /* PCIe Root Ports */
 144         /* PCIe output clocks type to PCIe devices.
 145          * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 146          * 0xFF: not used */
 147         uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
 148         /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 149          * clksrc. */
 150         uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
 151
 152         /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 153         bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 154
 155         /* PCIe LTR: Enable (1) / Disable (0) */
 156         uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
 157
 158         /* PCIe RP L1 substate */
 159         enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 160
 161         /* PCIe ModPhy related */
 162         struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
 163
 164         /* SMBus */
 165         bool SmbusEnable;
 166
 167         /* eMMC and SD */
 168         bool ScsEmmcHs400Enabled;
 169
 170         /* Enable if SD Card Power Enable Signal is Active High */
 171         bool SdCardPowerEnableActiveHigh;
 172
 173         /* VR Config Settings for IA Core */
 174         uint16_t ImonSlope;
 175         uint16_t ImonOffset;
 176
 177         /* Gfx related */
 178         bool SkipExtGfxScan;
 179
 180         bool eist_enable;
 181
 182         /* Enable C6 DRAM */
 183         bool enable_c6dram;
 184
 185         /*
 186          * SerialIO device mode selection:
 187          * PchSerialIoDisabled,
 188          * PchSerialIoPci,
 189          * PchSerialIoHidden,
 190          * PchSerialIoLegacyUart,
 191          * PchSerialIoSkipInit
 192          */
 193         uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 194         uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 195         uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
 196         /*
 197          * GSPIn Default Chip Select Mode:
 198          * 0:Hardware Mode,
 199          * 1:Software Mode
 200          */
 201         uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 202         /*
 203          * GSPIn Default Chip Select State:
 204          * 0: Low,
 205          * 1: High
 206          */
 207         uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 208
 209         /*
 210          * TraceHubMode config
 211          * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
 212          */
 213         uint8_t TraceHubMode;
 214
 215         /* Debug interface selection */
 216         enum {
 217                 DEBUG_INTERFACE_RAM = (1 << 0),
 218                 DEBUG_INTERFACE_UART_8250IO = (1 << 1),
 219                 DEBUG_INTERFACE_USB3 = (1 << 3),
 220                 DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
 221                 DEBUG_INTERFACE_TRACEHUB = (1 << 5),
 222         } debug_interface_flag;
 223
 224         /* GPIO SD card detect pin */
 225         unsigned int sdcard_cd_gpio;
 226
 227         /* Enable Pch iSCLK */
 228         bool pch_isclk;
 229
 230         /* Tcss */
 231         bool TcssXhciEn;
 232         bool TcssXdciEn;
 233
 234         /*
 235          * Override GPIO PM configuration:
 236          * false: Use FSP default GPIO PM program,
 237          * true: coreboot to override GPIO PM program
 238          */
 239         bool gpio_override_pm;
 240
 241         /*
 242          * GPIO PM configuration: 0 to disable, 1 to enable power gating
 243          * Bit 6-7: Reserved
 244          * Bit 5: MISCCFG_GPSIDEDPCGEN
 245          * Bit 4: MISCCFG_GPRCOMPCDLCGEN
 246          * Bit 3: MISCCFG_GPRTCDLCGEN
 247          * Bit 2: MISCCFG_GSXLCGEN
 248          * Bit 1: MISCCFG_GPDPCGEN
 249          * Bit 0: MISCCFG_GPDLCGEN
 250          */
 251         uint8_t gpio_pm[TOTAL_GPIO_COMM];
 252
 253         /* DP config */
 254         /*
 255          * Port config
 256          * 0:Disabled, 1:eDP, 2:MIPI DSI
 257          */
 258         uint8_t DdiPortAConfig;
 259         uint8_t DdiPortBConfig;
 260
 261         /*
 262          * HDP config
 263          */
 264         bool DdiPortAHpd;
 265         bool DdiPortBHpd;
 266         bool DdiPortCHpd;
 267         bool DdiPort1Hpd;
 268         bool DdiPort2Hpd;
 269         bool DdiPort3Hpd;
 270         bool DdiPort4Hpd;
 271
 272         /*
 273          * DDC config
 274          */
 275         bool DdiPortADdc;
 276         bool DdiPortBDdc;
 277         bool DdiPortCDdc;
 278         bool DdiPort1Ddc;
 279         bool DdiPort2Ddc;
 280         bool DdiPort3Ddc;
 281         bool DdiPort4Ddc;
 282
 283         /* Hybrid storage mode
 284          * This mode makes FSP detect Optane and NVME and set PCIe lane mode
 285          * accordingly
 286          *
 287          * true: Enable Hybrid storage mode
 288          * false Dsiable Hybrid storage mode
 289          */
 290         bool HybridStorageMode;
 291
 292         /*
 293          * Override CPU flex ratio value:
 294          * CPU ratio value controls the maximum processor non-turbo ratio.
 295          * Valid Range 0 to 63.
 296          * In general descriptor provides option to set default cpu flex ratio.
 297          * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
 298          * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
 299          * Only override CPU flex ratio to not boot with non-turbo max.
 300          */
 301         uint8_t cpu_ratio_override;
 302
 303         /* Skip CPU replacement check
 304          *
 305          * Setting this option to skip CPU replacement check to avoid the forced MRC training
 306          * for the platforms with soldered down SOC.
 307          *
 308          * false: disable
 309          * true: enable
 310          */
 311         bool SkipCpuReplacementCheck;
 312
 313         /*
 314          * SLP_S3 Minimum Assertion Width Policy
 315          *  1 = 60us
 316          *  2 = 1ms
 317          *  3 = 50ms (default)
 318          *  4 = 2s
 319          */
 320         uint8_t PchPmSlpS3MinAssert;
 321
 322         /*
 323          * SLP_S4 Minimum Assertion Width Policy
 324          *  1 = 1s (default)
 325          *  2 = 2s
 326          *  3 = 3s
 327          *  4 = 4s
 328          */
 329         uint8_t PchPmSlpS4MinAssert;
 330
 331         /*
 332          * SLP_SUS Minimum Assertion Width Policy
 333          *  1 = 0ms
 334          *  2 = 500ms
 335          *  3 = 1s
 336          *  4 = 4s (default)
 337          */
 338         uint8_t PchPmSlpSusMinAssert;
 339
 340         /*
 341          * SLP_A Minimum Assertion Width Policy
 342          *  1 = 0ms
 343          *  2 = 4s
 344          *  3 = 98ms
 345          *  4 = 2s (default)
 346          */
 347         uint8_t PchPmSlpAMinAssert;
 348
 349         /*
 350          * PCH PM Reset Power Cycle Duration
 351          *  0 = 4s (default)
 352          *  1 = 1s
 353          *  2 = 2s
 354          *  3 = 3s
 355          *  4 = 4s
 356          *
 357          * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
 358          * stretch duration programmed in the following registers:
 359          *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
 360          *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
 361          *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
 362          *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 363          */
 364         uint8_t PchPmPwrCycDur;
 365
 366         /*
 367          * FIVR RFI Frequency
 368          * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
 369          * 0: Auto.
 370          * Range varies based on XTAL clock:
 371          *    0-1918 (Up to 191.8HMz) for 24MHz clock;
 372          *    0-1535 (Up to 153.5MHz) for 19MHz clock.
 373          */
 374         uint16_t FivrRfiFrequency;
 375
 376         /*
 377          * FIVR RFI Spread Spectrum
 378          * Set the Spread Spectrum Range. <b>0: 0%</b>;
 379          * FIVR RFI Spread Spectrum, in 0.1% increments.
 380          * Range: 0.0% to 10.0% (0-100)
 381          */
 382         uint8_t FivrSpreadSpectrum;
 383
 384         /*
 385          * Disable Fast Slew Rate for Deep Package C States for VCCIN VR domain
 386          * Disable Fast Slew Rate for Deep Package C States based on
 387          * Acoustic Noise Mitigation feature enabled.
 388          */
 389         bool FastPkgCRampDisable;
 390
 391         /*
 392          * Slew Rate configuration for Deep Package C States for VCCIN VR domain
 393          * based on Acoustic Noise Mitigation feature enabled.
 394          * 0: Fast/2 ; 1: Fast/4; 2: Fast/8; 3: Fast/16
 395          */
 396         enum {
 397                 SlewRateFastBy2 = 0,
 398                 SlewRateFastBy4,
 399                 SlewRateFastBy8,
 400                 SlewRateFastBy16
 401         } SlowSlewRate;
 402
 403         /*
 404          * Enable or Disable Acoustic Noise Mitigation feature.
 405          */
 406         bool AcousticNoiseMitigation;
 407
 408         /*
 409          * Acoustic Noise Mitigation Range.Defines the maximum Pre-Wake
 410          * randomization time in micro ticks.This can be programmed only
 411          * if AcousticNoiseMitigation is enabled.
 412          * Range 0-255
 413          */
 414         uint8_t PreWake;
 415
 416         /*
 417          * Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
 418          * randomization time in micro ticks.This can be programmed only
 419          * if AcousticNoiseMitigation is enabled.
 420          * Range 0-255
 421          */
 422         uint8_t RampUp;
 423
 424         /*
 425          * Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
 426          * randomization time in micro ticks.This can be programmed only
 427          * if AcousticNoiseMitigation is enabled.
 428          * Range 0-255
 429          */
 430         uint8_t RampDown;
 431
 432         /*
 433          * It controls below soc variables
 434          *
 435          *   PchFivrExtV1p05RailEnabledStates
 436          *   PchFivrExtVnnRailSxEnabledStates
 437          *   PchFivrExtVnnRailEnabledStates
 438          *
 439          * If your platform does not support external vnn power rail please set to 1
 440          * 1: Disabled ; 0: Enabled
 441          */
 442         bool disable_external_bypass_vr;
 443
 444         /*
 445          * Core Display Clock Frequency selection, FSP UPD CdClock values + 1
 446          *
 447          * FSP will use the value to program clock frequency for core display if GOP
 448          * is not run. Ex: the Chromebook normal mode.
 449          * For the cases GOP is run, GOP will be in charge of the related register
 450          * settings.
 451          */
 452         enum {
 453                 CD_CLOCK_172_8_MHZ = 1,
 454                 CD_CLOCK_180_MHZ   = 2,
 455                 CD_CLOCK_192_MHZ   = 3,
 456                 CD_CLOCK_307_MHZ   = 4,
 457                 CD_CLOCK_312_MHZ   = 5,
 458                 CD_CLOCK_552_MHZ   = 6,
 459                 CD_CLOCK_556_8_MHZ = 7,
 460         } cd_clock;
 461
 462         /* Platform Power Pmax */
 463         uint16_t PsysPmax;
 464
 465         /*
 466          * This is a workaround to mitigate higher SoC power consumption in S0ix
 467          * when the CNVI has background activity.
 468          *
 469          * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
 470          * cppmvric1 register to 0) will break CNVI timing.
 471          * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and
 472          * AX201 (HrP2)
 473          *
 474          * true: Enabled (fewer wakes, lower power)
 475          * false: Disabled (more wakes, higher power)
 476          */
 477         bool cnvi_reduce_s0ix_pwr_usage;
 478
 479         /* i915 struct for GMA backlight control */
 480         struct i915_gpu_controller_info gfx;
 481 };
 482
 483 typedef struct soc_intel_jasperlake_config config_t;
 484
 485 #endif