| blob | 24d28f3b63d20824e2520318e17f67db18125b5e |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <intelblocks/tcss.h>
4 #include <soc/iomap.h>
6 /*
7 * Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
8 * USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers.
9 * PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1.
10 */
11 #define TCSS_TBT_PCIE0_RP0 0
12 #define TCSS_TBT_PCIE0_RP1 1
13 #define TCSS_TBT_PCIE0_RP2 2
14 #define TCSS_TBT_PCIE0_RP3 3
15 #define TCSS_XHCI 4
16 #define TCSS_XDCI 5
17 #define TCSS_DMA0 6
18 #define TCSS_DMA1 7
20 /*
21 * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
22 * Command code 0x15
23 * Description: Gateway command for handling TCSS DEVEN clear/restore.
24 * Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from
25 * a pre-defined set of subcommands.
26 */
27 #define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015
28 #define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */
29 #define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */
30 #define TCSS_IOM_ACK_TIMEOUT_IN_MS 100
32 #define MCHBAR_TCSS_DEVEN_OFFSET 0x7090
34 #define REVISION_ID 1
35 #define UNRECOGNIZED_UUID 0x4
36 #define UNRECOGNIZED_REVISION 0x8
38 #define USB_TUNNELING 0x1
39 #define DISPLAY_PORT_TUNNELING 0x2
40 #define PCIE_TUNNELING 0x4
41 #define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8
43 Scope (\_SB)
44 {
45 /* Device base address */
46 Method (BASE, 1)
47 {
48 Local0 = Arg0 & 0x7 /* Function number */
49 Local1 = (Arg0 >> 16) & 0x1F /* Device number */
50 Local2 = (Local0 << 12) + (Local1 << 15)
51 Local3 = \_SB.PCI0.GPCB() + Local2
52 Return (Local3)
53 }
55 /*
56 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
57 * found in Device 31, Function 2, Offset 40h.
58 */
59 OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80)
60 Field (PMIO, ByteAcc, NoLock, Preserve) {
61 Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */
62 , 19,
63 CPWS, 1, /* CPU WAKE STATUS */
64 Offset(0x7C), /* 0x7C, General Purpose Event 0 Enable [127:96] */
65 , 19,
66 CPWE, 1 /* CPU WAKE EN */
67 }
69 Name (C2PW, 0) /* Set default value to 0. */
71 /*
72 * C2PM (CPU to PCH Method)
73 *
74 * This object is Enable/Disable GPE_CPU_WAKE_EN.
75 * Arguments: (4)
76 * Arg0 - An Integer containing the device wake capability
77 * Arg1 - An Integer containing the target system state
78 * Arg2 - An Integer containing the target device state
79 * Arg3 - An Integer containing the request device type
80 * Return Value:
81 * return 0
82 */
83 Method (C2PM, 4, NotSerialized)
84 {
85 Local0 = 1 << Arg3
86 /* This method is used to enable/disable wake from Tcss Device (WKEN). */
87 If (Arg0 && Arg1)
88 { /* If entering Sx and enabling wake, need to enable WAKE capability. */
89 If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */
90 If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */
91 /* Clear CPU WAKE STATUS by writing 1. */
92 CPWS = 1
93 }
94 CPWE = 1 /* Set CPU WAKE EN by writing 1. */
95 }
96 If ((C2PW & Local0) == 0) {
97 /* Set Corresponding Device En BIT in C2PW. */
98 C2PW |= Local0
99 }
100 } Else { /* If Staying in S0 or Disabling Wake. */
101 If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */
102 /* If CPU WAKE EN is not set, Set it. */
103 If (CPWE == 0) {
104 /* If CPU WAKE STATUS is set, Clear it. */
105 If (CPWS) {
106 /* Clear CPU WAKE STATUS by writing 1. */
107 CPWS = 1
108 }
109 CPWE = 1 /* Set CPU WAKE EN by writing 1. */
110 }
111 If ((C2PW & Local0) == 0) {
112 /* Set Corresponding Device En BIT in C2PW. */
113 C2PW |= Local0
114 }
115 } Else {
116 /*
117 * Disable runtime PME, either because staying in D0 or
118 * disabling wake.
119 */
120 If ((C2PW & Local0) != 0) {
121 /*
122 * Clear Corresponding Device En BIT in C2PW.
123 */
124 C2PW &= ~Local0
125 }
126 If ((CPWE != 0) && (C2PW == 0)) {
127 /*
128 * If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN
129 * by writing 0.
130 */
131 CPWE = 0
132 }
133 }
134 }
135 Return (0)
136 }
138 Method (_OSC, 4, Serialized)
139 {
140 CreateDWordField (Arg3, 0, CDW1)
141 If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) {
142 /* Platform-Wide _OSC Capabilities
143 * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48}
144 * Arg1: Revision ID = 1
145 * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3
146 * Arg3: DWORD capabilities buffer:
147 * First DWORD: The standard definition bits are used to return errors.
148 * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities
149 * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4
150 * support. The OS sets this bit to indicate support for an OSPM-native
151 * USB4 Connection Manager which handles USB4 connection events and
152 * link management.
153 */
154 If (Arg1 != REVISION_ID) {
155 CDW1 |= UNRECOGNIZED_REVISION
156 }
157 Return (Arg3)
158 #if CONFIG(SOFTWARE_CONNECTION_MANAGER)
159 /*
160 * Software Connection Manager doesn't work with Linux 5.13 or later and
161 * results in TBT ports timing out. Not advertising this results in
162 * Firmware Connection Manager being used and TBT works correctly.
163 */
164 } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) {
165 /*
166 * Operating System Capabilities for USB4
167 * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A}
168 * Arg1: Revision ID = 1
169 * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3
170 * Arg3: DWORD capabilities buffer:
171 * First DWORD: The standard definition bits are used to return errors.
172 * Second DWORD: OSPM support field for USB4, bits [31:0] reserved.
173 * Third DWORD: OSPM control field for USB4.
174 * bit 0: USB tunneling
175 * bit 1: DisplayPort tunneling
176 * bit 2: PCIe tunneling
177 * bit 3: Inter-domain USB4 internet protocol
178 * bit 31:4: reserved
179 * Return: The platform acknowledges the capabilities buffer by
180 * returning a buffer of DWORD of the same length. Masked/Cleared bits
181 * in the control field indicate that the platform does not permit OSPM
182 * control of the respectively capabilities or features.
183 */
184 CreateDWordField (Arg3, 8, CDW3)
185 Local0 = CDW3
187 If (Arg1 != REVISION_ID) {
188 CDW1 |= UNRECOGNIZED_REVISION
189 Return (Arg3)
190 }
191 Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING |
192 INTER_DOMAIN_USB4_INTERNET_PROTOCOL
193 CDW3 = Local0
194 Return (Arg3)
195 #endif
196 } Else {
197 CDW1 |= UNRECOGNIZED_UUID
198 Return (Arg3)
199 }
200 }
201 }
203 Scope (_GPE)
204 {
205 /* PCI Express Hot-Plug wake event */
206 Method (_L61, 0, NotSerialized)
207 {
208 /*
209 * Delay for 100ms to meet the timing requirements of the PCI Express Base
210 * Specification, Revision 1.0A, Section 6.6 ("...software must wait at least
211 * 100ms from the end of reset of one or more device before it is permitted
212 * to issue Configuration Requests to those devices").
213 */
214 Sleep (100)
216 If (CondRefOf (\_SB.PCI0.TXHC)) {
217 /* Invoke PCIe root ports wake event handler */
218 \_SB.PCI0.TRP0.HPEV()
219 \_SB.PCI0.TRP1.HPEV()
220 \_SB.PCI0.TRP2.HPEV()
221 \_SB.PCI0.TRP3.HPEV()
222 }
224 /* Check Root Port 0 for a Hot Plug Event if the port is enabled */
225 If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) {
226 If (\_SB.PCI0.TRP0.PDCX) {
227 /* Clear all status bits */
228 \_SB.PCI0.TRP0.PDCX = 1
229 \_SB.PCI0.TRP0.HPSX = 1
230 /*
231 * Intercept Presence Detect Changed interrupt and make sure
232 * the L0s is disabled on empty slots.
233 */
234 If (!\_SB.PCI0.TRP0.PDSX) {
235 /*
236 * The PCIe slot is empty, so disable L0s on hot unplug.
237 */
238 \_SB.PCI0.TRP0.L0SE = 0
239 }
240 /* Performs proper notification to the OS. */
241 Notify (\_SB.PCI0.TRP0, 0)
242 } Else {
243 /* False event. Clear Hot-Plug status, then exit. */
244 \_SB.PCI0.TRP0.HPSX = 1
245 }
246 }
248 /* Check Root Port 1 for a Hot Plug Event if the port is enabled */
249 If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) {
250 If (\_SB.PCI0.TRP1.PDCX) {
251 \_SB.PCI0.TRP1.PDCX = 1
252 \_SB.PCI0.TRP1.HPSX = 1
253 If (!\_SB.PCI0.TRP1.PDSX) {
254 \_SB.PCI0.TRP1.L0SE = 0
255 }
256 Notify (\_SB.PCI0.TRP1, 0)
257 } Else {
258 \_SB.PCI0.TRP1.HPSX = 1
259 }
260 }
262 /* Check Root Port 2 for a Hot Plug Event if the port is enabled */
263 If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) {
264 If (\_SB.PCI0.TRP2.PDCX) {
265 \_SB.PCI0.TRP2.PDCX = 1
266 \_SB.PCI0.TRP2.HPSX = 1
267 If (!\_SB.PCI0.TRP2.PDSX) {
268 \_SB.PCI0.TRP2.L0SE = 0
269 }
270 Notify (\_SB.PCI0.TRP2, 0)
271 } Else {
272 \_SB.PCI0.TRP2.HPSX = 1
273 }
274 }
276 /* Check Root Port 3 for a Hot Plug Event if the port is enabled */
277 If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) {
278 If (\_SB.PCI0.TRP3.PDCX) {
279 \_SB.PCI0.TRP3.PDCX = 1
280 \_SB.PCI0.TRP3.HPSX = 1
281 If (!\_SB.PCI0.TRP3.PDSX) {
282 \_SB.PCI0.TRP3.L0SE = 0
283 }
284 Notify (\_SB.PCI0.TRP3, 0)
285 } Else {
286 \_SB.PCI0.TRP3.HPSX = 1
287 }
288 }
289 }
291 /* PCI Express power management event */
292 Method (_L69, 0, Serialized)
293 {
294 If (CondRefOf (\_SB.PCI0.TXHC)) {
295 If (\_SB.PCI0.TRP0.HPME() == 1) {
296 Notify (\_SB.PCI0.TDM0, 0x2)
297 Notify (\_SB.PCI0.TRP0, 0x2)
298 }
300 If (\_SB.PCI0.TRP1.HPME() == 1) {
301 Notify (\_SB.PCI0.TDM0, 0x2)
302 Notify (\_SB.PCI0.TRP1, 0x2)
303 }
305 If (\_SB.PCI0.TRP2.HPME() == 1) {
306 Notify (\_SB.PCI0.TDM1, 0x2)
307 Notify (\_SB.PCI0.TRP2, 0x2)
308 }
310 If (\_SB.PCI0.TRP3.HPME() == 1) {
311 Notify (\_SB.PCI0.TDM1, 0x2)
312 Notify (\_SB.PCI0.TRP3, 0x2)
313 }
314 }
316 /* Invoke PCIe root ports power management status handler */
317 \_SB.PCI0.TRP0.HPME()
318 \_SB.PCI0.TRP1.HPME()
319 \_SB.PCI0.TRP2.HPME()
320 \_SB.PCI0.TRP3.HPME()
321 }
322 }
324 Scope (\_SB.PCI0)
325 {
326 Device (IOM)
327 {
328 Name (_HID, "INTC107A")
329 Name (_DDN, "Intel(R) Meteor Lake Input Output Manager(IOM) driver")
330 /* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */
331 Name (_CRS, ResourceTemplate () {
332 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
333 NonCacheable, ReadWrite, 0x0,
334 IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0,
335 IOM_BASE_SIZE,,,)
336 })
337 /* Hide the device so that Windows does not complain on missing driver */
338 Name (_STA, 0xB)
339 }
341 /*
342 * Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
343 * 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.
344 */
345 OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4)
346 Field (TDEN, ByteAcc, NoLock, Preserve)
347 {
348 TRE0, 1, /* PCIE0_EN */
349 TRE1, 1, /* PCIE1_EN */
350 TRE2, 1, /* PCIE2_EN */
351 TRE3, 1, /* PCIE3_EN */
352 , 4,
353 THCE, 1, /* XHCI_EN */
354 TDCE, 1, /* XDCI_EN */
355 DME0, 1, /* TBT_DMA0_EN */
356 DME1, 1, /* TBT_DMA1_EN */
357 , 20
358 }
360 /*
361 * Operation region defined to access the pCode mailbox interface. Get the MCHBAR
362 * in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR.
363 */
364 OperationRegion (PBAR, SystemMemory, (GMHB() + 0x5DA0), 0x08)
365 Field (PBAR, DWordAcc, NoLock, Preserve)
366 {
367 PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */
368 PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */
369 PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */
370 , 15, /* Reserved */
371 PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */
372 }
374 /*
375 * Poll pCode MailBox Ready
376 *
377 * Return 0xFF - Timeout
378 * 0x00 - Ready
379 */
380 Method (PMBY, 0)
381 {
382 Local0 = 0
383 While (PMBR && (Local0 < 1000)) {
384 Local0++
385 Stall (1)
386 }
387 If (Local0 == 1000) {
388 Printf("Timeout occurred.")
389 Return (0xFF)
390 }
391 Return (0)
392 }
395 /*
396 * From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where
397 * 0x40 is the register offset.
398 */
399 OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)
400 Field (IOMR, DWordAcc, NoLock, Preserve)
401 {
402 Offset(0x40),
403 , 15,
404 TD3C, 1, /* [15:15] Type C D3 cold bit */
405 TACK, 1, /* [16:16] IOM Acknowledge bit */
406 DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */
407 /* display is OFF, clear otherwise */
408 Offset(0x70), /* Physical addr is offset 0x70. */
409 IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
410 IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
411 }
413 /*
414 * TBT Group0 ON method
415 */
416 Method (TG0N, 0)
417 {
418 If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
419 Printf("TDM0 does not exist.")
420 } Else {
421 If (\_SB.PCI0.TDM0.STAT == 0) {
422 /* DMA0 is in D3Cold early. */
423 \_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */
425 Printf("Bring TBT RPs out of D3Code.")
426 If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
427 /* RP0 D3 cold exit. */
428 \_SB.PCI0.TRP0.D3CX()
429 }
430 If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
431 /* RP1 D3 cold exit. */
432 \_SB.PCI0.TRP1.D3CX()
433 }
434 } Else {
435 Printf("Drop TG0N due to it is already exit D3 cold.")
436 }
438 /* TBT RTD3 exit 10ms delay. */
439 Sleep (10)
440 }
441 }
443 /*
444 * TBT Group0 OFF method
445 */
446 Method (TG0F, 0)
447 {
448 If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
449 Printf("TDM0 does not exist.")
450 } Else {
451 If (\_SB.PCI0.TDM0.STAT == 1) {
452 /* DMA0 is not in D3Cold now. */
453 \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
455 Printf("Push TBT RPs to D3Cold together")
456 If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
457 /* Put RP0 to D3 cold. */
458 \_SB.PCI0.TRP0.D3CE()
459 }
460 If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
461 /* Put RP1 to D3 cold. */
462 \_SB.PCI0.TRP1.D3CE()
463 }
464 }
465 }
466 }
468 /*
469 * TBT Group1 ON method
470 */
471 Method (TG1N, 0)
472 {
473 If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
474 Printf("TDM1 does not exist.")
475 } Else {
476 If (\_SB.PCI0.TDM1.STAT == 0) {
477 /* DMA1 is in D3Cold early. */
478 \_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */
480 Printf("Bring TBT RPs out of D3Code.")
481 If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
482 /* RP2 D3 cold exit. */
483 \_SB.PCI0.TRP2.D3CX()
484 }
485 If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
486 /* RP3 D3 cold exit. */
487 \_SB.PCI0.TRP3.D3CX()
488 }
489 } Else {
490 Printf("Drop TG1N due to it is already exit D3 cold.")
491 }
493 /* TBT RTD3 exit 10ms delay. */
494 Sleep (10)
495 }
496 }
498 /*
499 * TBT Group1 OFF method
500 */
501 Method (TG1F, 0)
502 {
503 If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
504 Printf("TDM1 does not exist.")
505 } Else {
506 If (\_SB.PCI0.TDM1.STAT == 1) {
507 /* DMA1 is not in D3Cold now */
508 \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
510 Printf("Push TBT RPs to D3Cold together")
511 If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
512 /* Put RP2 to D3 cold. */
513 \_SB.PCI0.TRP2.D3CE()
514 }
515 If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
516 /* Put RP3 to D3 cold */
517 \_SB.PCI0.TRP3.D3CE()
518 }
519 }
520 }
521 }
523 PowerResource (TBT0, 5, 1)
524 {
525 Method (_STA, 0)
526 {
527 Return (\_SB.PCI0.TDM0.STAT)
528 }
530 Method (_ON, 0)
531 {
532 TG0N()
533 }
535 Method (_OFF, 0)
536 {
537 If (\_SB.PCI0.TDM0.SD3C == 0) {
538 TG0F()
539 }
540 }
541 }
543 PowerResource (TBT1, 5, 1)
544 {
545 Method (_STA, 0)
546 {
547 Return (\_SB.PCI0.TDM1.STAT)
548 }
550 Method (_ON, 0)
551 {
552 TG1N()
553 }
555 Method (_OFF, 0)
556 {
557 If (\_SB.PCI0.TDM1.SD3C == 0) {
558 TG1F()
559 }
560 }
561 }
563 #if CONFIG(D3COLD_SUPPORT)
564 Method (TCON, 0)
565 {
566 /* Reset IOM D3 cold bit if it is in D3 cold now. */
567 If (TD3C == 1) /* It was in D3 cold before. */
568 {
569 /* Reset IOM D3 cold bit. */
570 TD3C = 0 /* Request IOM for D3 cold exit sequence. */
571 Local0 = 0 /* Time check counter variable */
572 /* Wait for ack, the maximum wait time for the ack is 100 msec. */
573 While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) {
574 /*
575 * Wait in this loop until TACK becomes 0 with timeout
576 * TCSS_IOM_ACK_TIMEOUT_IN_MS by default.
577 */
578 Sleep (1) /* Delay of 1ms. */
579 Local0++
580 }
582 If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
583 Printf("Error: Timeout occurred.")
584 }
585 Else
586 {
587 Printf("TCSS D3 exit.");
588 }
589 }
590 Else {
591 Printf("Drop TCON due to it is already exit D3 cold.")
592 }
593 }
595 Method (TCOF, 0)
596 {
597 If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0)
598 || (\_SB.PCI0.TDM1.SD3C != 0))
599 {
600 Printf("Skip D3C entry.")
601 Return
602 }
604 /* Request IOM for D3 cold entry sequence. */
605 TD3C = 1
606 }
608 PowerResource (D3C, 5, 0)
609 {
610 /*
611 * Variable to save power state
612 * 1 - TC Cold request cleared.
613 * 0 - TC Cold request sent.
614 */
615 Name (STAT, 0x1)
617 Method (_STA, 0)
618 {
619 Return (STAT)
620 }
622 Method (_ON, 0)
623 {
624 \_SB.PCI0.TCON()
625 STAT = 1
626 }
628 Method (_OFF, 0)
629 {
630 \_SB.PCI0.TCOF()
631 STAT = 0
632 }
633 }
634 #endif // D3COLD_SUPPORT
636 /*
637 * TCSS xHCI device
638 */
639 Device (TXHC)
640 {
641 Name (_ADR, 0x000D0000)
642 Name (_DDN, "North XHCI controller")
643 Name (_STR, Unicode ("North XHCI controller"))
644 Name (DCPM, TCSS_XHCI)
646 Method (_STA, 0x0, NotSerialized)
647 {
648 If (THCE == 1) {
649 Return (0x0F)
650 } Else {
651 Return (0x0)
652 }
653 }
654 #include "tcss_xhci.asl"
655 }
657 /*
658 * TCSS DMA0 device
659 */
660 Device (TDM0)
661 {
662 Name (_ADR, 0x000D0002)
663 Name (_DDN, "TBT DMA0 controller")
664 Name (_STR, Unicode ("TBT DMA0 controller"))
665 Name (DUID, 0) /* TBT DMA number */
666 Name (DCPM, TCSS_DMA0)
668 Method (_STA, 0x0, NotSerialized)
669 {
670 If (DME0 == 1) {
671 Return (0x0F)
672 } Else {
673 Return (0x0)
674 }
675 }
676 #include "tcss_dma.asl"
677 }
679 /*
680 * TCSS DMA1 device
681 */
682 Device (TDM1)
683 {
684 Name (_ADR, 0x000D0003)
685 Name (_DDN, "TBT DMA1 controller")
686 Name (_STR, Unicode ("TBT DMA1 controller"))
687 Name (DUID, 1) /* TBT DMA number */
688 Name (DCPM, TCSS_DMA1)
690 Method (_STA, 0x0, NotSerialized)
691 {
692 If (DME1 == 1) {
693 Return (0x0F)
694 } Else {
695 Return (0x0)
696 }
697 }
698 #include "tcss_dma.asl"
699 }
701 /*
702 * TCSS PCIE Root Port #00
703 */
704 Device (TRP0)
705 {
706 Name (_ADR, 0x00070000)
707 Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */
708 Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
709 Name (LMSL, 0) /* PCIE LTR max snoop Latency */
710 Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
711 Name (DCPM, TCSS_TBT_PCIE0_RP0)
713 Method (_STA, 0x0, NotSerialized)
714 {
715 If (VDID != 0xFFFFFFFF) {
716 Return (0x0F)
717 } Else {
718 Return (0x0)
719 }
720 }
722 Method (_INI)
723 {
724 LTEN = 0
725 LMSL = 0x88C8
726 LNSL = 0x88C8
727 }
728 #include "tcss_pcierp.asl"
729 }
731 /*
732 * TCSS PCIE Root Port #01
733 */
734 Device (TRP1)
735 {
736 Name (_ADR, 0x00070001)
737 Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */
738 Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
739 Name (LMSL, 0) /* PCIE LTR max snoop Latency */
740 Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
741 Name (DCPM, TCSS_TBT_PCIE0_RP1)
743 Method (_STA, 0x0, NotSerialized)
744 {
745 If (VDID != 0xFFFFFFFF) {
746 Return (0x0F)
747 } Else {
748 Return (0x0)
749 }
750 }
752 Method (_INI)
753 {
754 LTEN = 0
755 LMSL = 0x88C8
756 LNSL = 0x88C8
757 }
758 #include "tcss_pcierp.asl"
759 }
761 /*
762 * TCSS PCIE Root Port #02
763 */
764 Device (TRP2)
765 {
766 Name (_ADR, 0x00070002)
767 Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */
768 Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
769 Name (LMSL, 0) /* PCIE LTR max snoop Latency */
770 Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
771 Name (DCPM, TCSS_TBT_PCIE0_RP2)
773 Method (_STA, 0x0, NotSerialized)
774 {
775 If (VDID != 0xFFFFFFFF) {
776 Return (0x0F)
777 } Else {
778 Return (0x0)
779 }
780 }
782 Method (_INI)
783 {
784 LTEN = 0
785 LMSL = 0x88C8
786 LNSL = 0x88C8
787 }
788 #include "tcss_pcierp.asl"
789 }
791 /*
792 * TCSS PCIE Root Port #03
793 */
794 Device (TRP3)
795 {
796 Name (_ADR, 0x00070003)
797 Name (TUID, 3) /* TBT PCIE RP Number 3 for RP03 */
798 Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
799 Name (LMSL, 0) /* PCIE LTR max snoop Latency */
800 Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
801 Name (DCPM, TCSS_TBT_PCIE0_RP3)
803 Method (_STA, 0x0, NotSerialized)
804 {
805 If (VDID != 0xFFFFFFFF) {
806 Return (0x0F)
807 } Else {
808 Return (0x0)
809 }
810 }
812 Method (_INI)
813 {
814 LTEN = 0
815 LMSL = 0x88C8
816 LNSL = 0x88C8
817 }
818 #include "tcss_pcierp.asl"
819 }
820 }