src/soc/intel/meteorlake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_CHIP_H_
   4 #define _SOC_CHIP_H_
   5
   6 #include <drivers/i2c/designware/dw_i2c.h>
   7 #include <drivers/intel/gma/gma.h>
   8 #include <device/pci_ids.h>
   9 #include <gpio.h>
  10 #include <intelblocks/cfg.h>
  11 #include <intelblocks/gspi.h>
  12 #include <intelblocks/power_limit.h>
  13 #include <intelblocks/pcie_rp.h>
  14 #include <intelblocks/tcss.h>
  15 #include <soc/gpe.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/pmc.h>
  18 #include <soc/serialio.h>
  19 #include <soc/usb.h>
  20 #include <stdbool.h>
  21 #include <stdint.h>
  22
  23 /* Define config parameters for In-Band ECC (IBECC). */
  24 #define MAX_IBECC_REGIONS 8
  25
  26 #define MAX_SAGV_POINTS 4
  27 #define MAX_HD_AUDIO_SDI_LINKS 2
  28
  29 /* In-Band ECC Operation Mode */
  30 enum ibecc_mode {
  31         IBECC_MODE_PER_REGION,
  32         IBECC_MODE_NONE,
  33         IBECC_MODE_ALL
  34 };
  35
  36 struct ibecc_config {
  37         bool enable;
  38         bool parity_en;
  39         enum ibecc_mode mode;
  40         bool region_enable[MAX_IBECC_REGIONS];
  41         uint16_t region_base[MAX_IBECC_REGIONS];
  42         uint16_t region_mask[MAX_IBECC_REGIONS];
  43 };
  44
  45 /* Types of different SKUs */
  46 enum soc_intel_meteorlake_power_limits {
  47         MTL_P_282_242_CORE,
  48         MTL_P_682_482_CORE,
  49         MTL_POWER_LIMITS_COUNT
  50 };
  51
  52 /* TDP values for different SKUs */
  53 enum soc_intel_meteorlake_cpu_tdps {
  54         TDP_15W = 15,
  55         TDP_28W = 28
  56 };
  57
  58 /* Mapping of different SKUs based on CPU ID and TDP values */
  59 static const struct {
  60         unsigned int cpu_id;
  61         enum soc_intel_meteorlake_power_limits limits;
  62         enum soc_intel_meteorlake_cpu_tdps cpu_tdp;
  63 } cpuid_to_mtl[] = {
  64         { PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W },
  65         { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W },
  66         { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W },
  67         { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W },
  68 };
  69
  70 /* Types of display ports */
  71 enum ddi_ports {
  72         DDI_PORT_A,
  73         DDI_PORT_B,
  74         DDI_PORT_C,
  75         DDI_PORT_1,
  76         DDI_PORT_2,
  77         DDI_PORT_3,
  78         DDI_PORT_4,
  79         DDI_PORT_COUNT,
  80 };
  81
  82 enum ddi_port_flags {
  83         DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
  84         DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
  85 };
  86
  87 /*
  88  * The Max Pkg Cstate
  89  * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10,
  90  * 254 - CPU Default , 255 - Auto.
  91  */
  92 enum pkgcstate_limit {
  93         LIMIT_C0_C1             = 0,
  94         LIMIT_C2                = 1,
  95         LIMIT_C3                = 2,
  96         LIMIT_C6                = 3,
  97         LIMIT_C7                = 4,
  98         LIMIT_C7S               = 5,
  99         LIMIT_C8                = 6,
 100         LIMIT_C9                = 7,
 101         LIMIT_C10               = 8,
 102         LIMIT_CPUDEFAULT        = 254,
 103         LIMIT_AUTO              = 255,
 104 };
 105
 106 /* Bit values for use in LpmStateEnableMask. */
 107 enum lpm_state_mask {
 108         LPM_S0i2_0 = BIT(0),
 109         LPM_S0i2_1 = BIT(1),
 110         LPM_S0i2_2 = BIT(2),
 111         LPM_S0i3_0 = BIT(3),
 112         LPM_S0i3_1 = BIT(4),
 113         LPM_S0i3_2 = BIT(5),
 114         LPM_S0i3_3 = BIT(6),
 115         LPM_S0i3_4 = BIT(7),
 116         LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
 117                      | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
 118 };
 119
 120 /*
 121  * As per definition from FSP header:
 122  * - [0] for IA
 123  * - [1] for GT
 124  * - [2] for SA
 125  * - [3] through [5] are reserved
 126  */
 127 enum vr_domain {
 128         VR_DOMAIN_IA,
 129         VR_DOMAIN_GT,
 130         VR_DOMAIN_SA,
 131         NUM_VR_DOMAINS
 132 };
 133
 134 /*
 135  * Slew Rate configuration for Deep Package C States for VR domain.
 136  * They are fast time divided by 2.
 137  * 0 - Fast/2
 138  * 1 - Fast/4
 139  * 2 - Fast/8
 140  * 3 - Fast/16
 141  */
 142 enum slew_rate {
 143         SLEW_FAST_2,
 144         SLEW_FAST_4,
 145         SLEW_FAST_8,
 146         SLEW_FAST_16,
 147         SLEW_IGNORE = 0xff,
 148 };
 149
 150 struct soc_intel_meteorlake_config {
 151         /* Common struct containing soc config data required by common code */
 152         struct soc_intel_common_config common_soc_config;
 153
 154         /* Common struct containing power limits configuration information */
 155         struct soc_power_limits_config power_limits_config[MTL_POWER_LIMITS_COUNT];
 156
 157         /* Gpio group routed to each dword of the GPE0 block. Values are
 158          * of the form PMC_GPP_[A:U] or GPD. */
 159         uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
 160         uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
 161         uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
 162
 163         /* Generic IO decode ranges */
 164         uint32_t gen1_dec;
 165         uint32_t gen2_dec;
 166         uint32_t gen3_dec;
 167         uint32_t gen4_dec;
 168
 169         /* Enable S0iX support */
 170         bool s0ix_enable;
 171         /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
 172         bool tcss_d3_hot_disable;
 173         /* Enable DPTF support */
 174         bool dptf_enable;
 175
 176         /* Deep SX enable for both AC and DC */
 177         bool deep_s3_enable_ac;
 178         bool deep_s3_enable_dc;
 179         bool deep_s5_enable_ac;
 180         bool deep_s5_enable_dc;
 181
 182         /* Deep Sx Configuration
 183          *  DSX_EN_WAKE_PIN       - Enable WAKE# pin
 184          *  DSX_EN_LAN_WAKE_PIN   - Enable LAN_WAKE# pin
 185          *  DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
 186         uint32_t deep_sx_config;
 187
 188         /* TCC activation offset */
 189         uint32_t tcc_offset;
 190
 191         /* In-Band ECC (IBECC) configuration */
 192         struct ibecc_config ibecc;
 193
 194         /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
 195          * When enabled memory will be training at two different frequencies.
 196          * 0:Disabled, 1:Enabled
 197          */
 198         enum {
 199                 SAGV_DISABLED,
 200                 SAGV_ENABLED,
 201         } sagv;
 202
 203         /* System Agent dynamic frequency work points that memory will be training
 204          * at the enabled frequencies. Possible work points are:
 205          * 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
 206          */
 207         enum {
 208                 SAGV_POINTS_0_1 = 0x03,
 209                 SAGV_POINTS_0_1_2 = 0x07,
 210                 SAGV_POINTS_0_1_2_3 = 0x0f,
 211         } sagv_wp_bitmap;
 212
 213         /* Rank Margin Tool. */
 214         bool rmt;
 215
 216         /* USB related */
 217         struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX];
 218         struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX];
 219         /* Wake Enable Bitmap for USB2 ports */
 220         uint16_t usb2_wake_enable_bitmap;
 221         /* Wake Enable Bitmap for USB3 ports */
 222         uint16_t usb3_wake_enable_bitmap;
 223         /* Program OC pins for TCSS */
 224         struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 225         /* Validate TBT firmware authenticated and loaded into IMR */
 226         bool tbt_authentication;
 227
 228         /* SATA related */
 229         uint8_t sata_mode;
 230         bool sata_salp_support;
 231         bool sata_ports_enable[8];
 232         bool sata_ports_dev_slp[8];
 233
 234         /*
 235          * Enable(false)/Disable(true) SATA Power Optimizer on PCH side.
 236          * Default false. Setting this to true disables the SATA Power Optimizer.
 237          */
 238         bool sata_pwr_optimize_disable;
 239
 240         /*
 241          * SATA Port Enable Dito Config.
 242          * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
 243          */
 244         bool sata_ports_enable_dito_config[8];
 245
 246         /* SataPortsDmVal is the DITO multiplier. Default is 15. */
 247         uint8_t sata_ports_dm_val[8];
 248         /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
 249         uint16_t sata_ports_dito_val[8];
 250
 251         /* Audio related */
 252         bool pch_hda_audio_link_hda_enable;
 253         bool pch_hda_dsp_enable;
 254
 255         bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
 256
 257         /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
 258         enum {
 259                 HDA_TMODE_2T = 0,
 260                 HDA_TMODE_4T = 2,
 261                 HDA_TMODE_8T = 3,
 262                 HDA_TMODE_16T = 4,
 263         } pch_hda_idisp_link_tmode;
 264
 265         /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
 266         enum {
 267                 HDA_LINKFREQ_48MHZ = 3,
 268                 HDA_LINKFREQ_96MHZ = 4,
 269         } pch_hda_idisp_link_frequency;
 270
 271         bool pch_hda_idisp_codec_enable;
 272
 273         struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS];
 274         uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
 275
 276         /* Gfx related */
 277         enum {
 278                 IGD_SM_0MB = 0x00,
 279                 IGD_SM_32MB = 0x01,
 280                 IGD_SM_64MB = 0x02,
 281                 IGD_SM_96MB = 0x03,
 282                 IGD_SM_128MB = 0x04,
 283                 IGD_SM_160MB = 0x05,
 284                 IGD_SM_4MB = 0xF0,
 285                 IGD_SM_8MB = 0xF1,
 286                 IGD_SM_12MB = 0xF2,
 287                 IGD_SM_16MB = 0xF3,
 288                 IGD_SM_20MB = 0xF4,
 289                 IGD_SM_24MB = 0xF5,
 290                 IGD_SM_28MB = 0xF6,
 291                 IGD_SM_36MB = 0xF8,
 292                 IGD_SM_40MB = 0xF9,
 293                 IGD_SM_44MB = 0xFA,
 294                 IGD_SM_48MB = 0xFB,
 295                 IGD_SM_52MB = 0xFC,
 296                 IGD_SM_56MB = 0xFD,
 297                 IGD_SM_60MB = 0xFE,
 298         } igd_dvmt50_pre_alloc;
 299
 300         bool skip_ext_gfx_scan;
 301         bool eist_enable;
 302
 303         /*
 304          * When enabled, this feature makes the SoC throttle when the power
 305          * consumption exceeds the I_TRIP threshold.
 306          *
 307          * FSPs sets a by default I_TRIP threshold adapted to the current SoC
 308          * and assuming a Voltage Regulator error accuracy of 6.5%.
 309          */
 310         bool enable_fast_vmode[NUM_VR_DOMAINS];
 311
 312         /*
 313          * Current Excursion Protection needs to be set for each VR domain
 314          * in order to be able to enable fast Vmode.
 315          */
 316         bool cep_enable[NUM_VR_DOMAINS];
 317
 318         /*
 319          * VR Fast Vmode I_TRIP threshold.
 320          * 0-255A in 1/4 A units. Example: 400 = 100A
 321          * This setting overrides the default value set by FSPs when Fast VMode
 322          * is enabled.
 323          */
 324         uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS];
 325
 326         /*
 327          * Power state current threshold 1.
 328          * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
 329          * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
 330          * SA, [3] through [5] are Reserved.
 331          */
 332         uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS];
 333
 334         /*
 335          * Power state current threshold 2.
 336          * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
 337          * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
 338          * SA, [3] through [5] are Reserved.
 339          */
 340         uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS];
 341
 342         /*
 343          * Power state current threshold 3.
 344          * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
 345          * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
 346          * SA, [3] through [5] are Reserved.
 347          */
 348         uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS];
 349
 350         /*
 351          * SerialIO device mode selection:
 352          * PchSerialIoDisabled,
 353          * PchSerialIoPci,
 354          * PchSerialIoHidden,
 355          * PchSerialIoLegacyUart,
 356          * PchSerialIoSkipInit
 357          */
 358         uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 359         uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 360         uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
 361         /*
 362          * GSPIn Default Chip Select Mode:
 363          * 0:Hardware Mode,
 364          * 1:Software Mode
 365          */
 366         uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 367         /*
 368          * GSPIn Default Chip Select State:
 369          * 0: Low,
 370          * 1: High
 371          */
 372         uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 373
 374         /* CNVi WiFi Core Enable/Disable */
 375         bool cnvi_wifi_core;
 376
 377         /* CNVi BT Core Enable/Disable */
 378         bool cnvi_bt_core;
 379
 380         /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 381         bool cnvi_bt_audio_offload;
 382
 383         /*
 384          * These GPIOs will be programmed by the IOM to handle biasing of the
 385          * Type-C aux (SBU) signals when certain alternate modes are used.
 386          * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
 387          * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
 388          * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
 389          * (name often contains `AUXP_DC` or `_AUX_P`).
 390          */
 391         struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
 392
 393         /*
 394          * SOC Aux orientation override:
 395          * This is a bitfield that corresponds to up to 4 TCSS ports on MTL.
 396          * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
 397          * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
 398          * on the motherboard.
 399          */
 400         uint16_t tcss_aux_ori;
 401
 402         /* Connect Topology Command timeout value */
 403         uint16_t itbt_connect_topology_timeout_in_ms;
 404
 405         /*
 406          * Override GPIO PM configuration:
 407          * 0: Use FSP default GPIO PM program,
 408          * 1: coreboot to override GPIO PM program
 409          */
 410         uint8_t gpio_override_pm;
 411
 412         /*
 413          * GPIO PM configuration: 0 to disable, 1 to enable power gating
 414          * Bit 6-7: Reserved
 415          * Bit 5: MISCCFG_GPSIDEDPCGEN
 416          * Bit 4: MISCCFG_GPRCOMPCDLCGEN
 417          * Bit 3: MISCCFG_GPRTCDLCGEN
 418          * Bit 2: MISCCFG_GSXLCGEN
 419          * Bit 1: MISCCFG_GPDPCGEN
 420          * Bit 0: MISCCFG_GPDLCGEN
 421          */
 422         uint8_t gpio_pm[TOTAL_GPIO_COMM];
 423
 424         /* DP config */
 425         /*
 426          * Port config
 427          * 0:Disabled, 1:eDP, 2:MIPI DSI
 428          */
 429         uint8_t ddi_port_A_config;
 430         uint8_t ddi_port_B_config;
 431
 432         /* Enable(1)/Disable(0) HPD/DDC */
 433         uint8_t ddi_ports_config[DDI_PORT_COUNT];
 434
 435         /*
 436          * Override CPU flex ratio value:
 437          * CPU ratio value controls the maximum processor non-turbo ratio.
 438          * Valid Range 0 to 63.
 439          *
 440          * In general descriptor provides option to set default cpu flex ratio.
 441          * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
 442          * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
 443          *
 444          * Only override CPU flex ratio if don't want to boot with non-turbo max.
 445          */
 446         uint8_t cpu_ratio_override;
 447
 448         /*
 449          * Enable(true)/Disable(false) DMI Power Optimizer on PCH side.
 450          * Default false. Setting this to true disables the DMI Power Optimizer.
 451          */
 452         bool dmi_pwr_optimize_disable;
 453
 454         /*
 455          * Enable(true)/Disable(false) CPU Replacement check.
 456          * Default false. Setting this to true to check CPU replacement.
 457          */
 458         bool cpu_replacement_check;
 459
 460         /* ISA Serial Base selection. */
 461         enum {
 462                 ISA_SERIAL_BASE_ADDR_3F8,
 463                 ISA_SERIAL_BASE_ADDR_2F8,
 464         } isa_serial_uart_base;
 465
 466         /*
 467          * Assign clock source port for GbE. 0: Disable, N-1: port number
 468          * Default 0.
 469          */
 470         uint8_t lan_clk;
 471
 472         /*
 473          * Enable or Disable C1 C-state Auto Demotion & un-demotion
 474          * The algorithm looks at the behavior of the wake up tracker, how
 475          * often it is waking up, and based on that it demote the c-state.
 476          * Default false. Set this to true in order to disable C1-state auto
 477          * demotion.
 478          * NOTE: Un-Demotion from Demoted C1 needs to be disabled when
 479          *       C1 C-state Auto Demotion is disabled.
 480          */
 481         bool disable_c1_state_auto_demotion;
 482
 483         /*
 484          * Enable or Disable Package C-state Demotion.
 485          * Default is set to false.
 486          * Set this to true in order to disable Package C-state demotion.
 487          * NOTE: Un-Demotion from demoted Package C-state needs to be disabled
 488          *       when auto demotion is disabled.
 489          */
 490         bool disable_package_c_state_demotion;
 491
 492         /* Enable PCH to CPU energy report feature. */
 493         bool pch_pm_energy_report_enable;
 494
 495         /* Energy-Performance Preference (HWP feature) */
 496         bool enable_energy_perf_pref;
 497         uint8_t energy_perf_pref_value;
 498
 499         bool disable_vmx;
 500
 501         /*
 502          * SAGV Frequency per point in Mhz. 0 is Auto, otherwise holds the
 503          * frequency value expressed as an integer. For example: 1867
 504          */
 505         uint16_t sagv_freq_mhz[MAX_SAGV_POINTS];
 506
 507         /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */
 508         uint8_t sagv_gear[MAX_SAGV_POINTS];
 509
 510         /*
 511          * Enable or Disable Reduced BasicMemoryTest size.
 512          * Default is set to false.
 513          * Set this to true in order to reduce BasicMemoryTest size
 514          */
 515         bool lower_basic_mem_test_size;
 516
 517         /* Platform Power Pmax in Watts. Zero means automatic. */
 518         uint16_t psys_pmax_watts;
 519
 520         /* Platform Power Limit 2 in Watts. */
 521         uint16_t psys_pl2_watts;
 522
 523         /* Enable or Disable Acoustic Noise Mitigation feature */
 524         bool enable_acoustic_noise_mitigation;
 525         /* Disable Fast Slew Rate for Deep Package C States for VR domains */
 526         bool disable_fast_pkgc_ramp[NUM_VR_DOMAINS];
 527         /*
 528          * Slew Rate configuration for Deep Package C States for VR domains
 529          * as per `enum slew_rate` data type.
 530          */
 531         uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
 532
 533         /* i915 struct for GMA backlight control */
 534         struct i915_gpu_controller_info gfx;
 535 };
 536
 537 typedef struct soc_intel_meteorlake_config config_t;
 538
 539 #endif